{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T07:58:05Z","timestamp":1761897485518,"version":"build-2065373602"},"reference-count":12,"publisher":"MDPI AG","issue":"4","license":[{"start":{"date-parts":[[2021,2,16]],"date-time":"2021-02-16T00:00:00Z","timestamp":1613433600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>This paper presents a digitally controlled oscillator (DCO) with a low-complexity circuit structure that combines multiple delay circuits to achieve a high timing resolution and wide output frequency range simultaneously while also significantly reducing the overall power consumption. A 0.18 \u00b5m complementary metal\u2013oxide\u2013semiconductor standard process was used for the design, and measurements showed that the chip had a minimum controllable timing resolution of 4.81 ps and power consumption of 142 \u00b5W with an output signal of 364 MHz. When compared with other designs using advanced processes, the proposed DCO demonstrated the best power-to-frequency ratio. Therefore, it can output a signal at the required frequency more efficiently in terms of power consumption. Additionally, because the proposed DCO uses digital logic gates only, a cell-based design flow can be implemented. Hence, the proposed DCO is not only easy to implement in different processes but also easy to integrate with other digital circuits.<\/jats:p>","DOI":"10.3390\/s21041377","type":"journal-article","created":{"date-parts":[[2021,2,16]],"date-time":"2021-02-16T08:09:09Z","timestamp":1613462949000},"page":"1377","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation"],"prefix":"10.3390","volume":"21","author":[{"given":"Duo","family":"Sheng","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Fu Jen Catholic University, New Taipei City 24205, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei-Yen","family":"Chen","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Fu Jen Catholic University, New Taipei City 24205, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hao-Ting","family":"Huang","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Fu Jen Catholic University, New Taipei City 24205, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Li","family":"Tai","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Fu Jen Catholic University, New Taipei City 24205, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2021,2,16]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"347","DOI":"10.1109\/JSSC.2002.807398","article-title":"An all digital phase-locked loop for high-speed clock generation","volume":"38","author":"Chung","year":"2003","journal-title":"IEEE J. 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Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), Taoyuan, Taiwan.","DOI":"10.1109\/ICCE-Taiwan49838.2020.9258210"},{"key":"ref_8","first-page":"673","article-title":"A low-power DCO using interlaced hysteresis delay cells","volume":"59","author":"Yu","year":"2012","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"Sheng, D., and Hong, M.-R. (2016). A low-power all-digital on-chip CMOS oscillator for a wireless sensor node. Sensors, 16.","DOI":"10.3390\/s16101710"},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"3369","DOI":"10.1109\/TVLSI.2017.2715167","article-title":"A process-independent and highly linear DCO for crowded heterogeneous IoT devices in 65-nm CMOS","volume":"25","author":"Gorji","year":"2017","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"054707","DOI":"10.1063\/1.5088214","article-title":"Dual-cell structure digitally controlled oscillator with portability for clock generation applications","volume":"90","author":"Sheng","year":"2019","journal-title":"Rev. Sci. Instrum."},{"key":"ref_12","doi-asserted-by":"crossref","first-page":"2212","DOI":"10.1109\/JSSC.2005.857370","article-title":"A monotonic digitally controlled delay element","volume":"40","author":"Sachdev","year":"2005","journal-title":"IEEE J. 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