{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T20:00:26Z","timestamp":1773777626229,"version":"3.50.1"},"reference-count":45,"publisher":"MDPI AG","issue":"13","license":[{"start":{"date-parts":[[2021,6,29]],"date-time":"2021-06-29T00:00:00Z","timestamp":1624924800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100014188","name":"Ministry of Science and ICT, South Korea","doi-asserted-by":"publisher","award":["2020-0-01304"],"award-info":[{"award-number":["2020-0-01304"]}],"id":[{"id":"10.13039\/501100014188","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 \u00d7 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm2 chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW\u201420 times lower than the digital implementation.<\/jats:p>","DOI":"10.3390\/s21134462","type":"journal-article","created":{"date-parts":[[2021,6,29]],"date-time":"2021-06-29T22:39:43Z","timestamp":1625006383000},"page":"4462","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":33,"title":["A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits"],"prefix":"10.3390","volume":"21","author":[{"given":"Malik Summair","family":"Asghar","sequence":"first","affiliation":[{"name":"Department of Electronics Engineering, Chungbuk National University, Chungdae-ro 1, Seowon-gu, Cheongju 28644, Korea"},{"name":"Department of Electrical and Computer Engineering, Abbottabad Campus, COMSATS University Islamabad, University Road, Tobe Camp, Abbottabad 22044, Pakistan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4038-462X","authenticated-orcid":false,"given":"Saad","family":"Arslan","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, COMSATS University Islamabad, Park Road, Tarlai Kalan, Islamabad 45550, Pakistan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hyungwon","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering, Chungbuk National University, Chungdae-ro 1, Seowon-gu, Cheongju 28644, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2021,6,29]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"1629","DOI":"10.1109\/5.58356","article-title":"Neuromorphic electronic systems","volume":"78","author":"Mead","year":"1990","journal-title":"Proc. IEEE"},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"61","DOI":"10.1038\/nature14441","article-title":"Training and operation of an integrated neuromorphic network based on metal-oxide memristors","volume":"521","author":"Prezioso","year":"2015","journal-title":"Nature"},{"key":"ref_3","unstructured":"Alex, K., Ilya, S., and Geoffrey, E.H. (2012, January 3\u20136). ImageNet classification with deep convolutional neural networks. Proceedings of the 25th International Conference on Neural Information Processing Systems, Lake Tahoe, NV, USA."},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"508","DOI":"10.3389\/fnins.2016.00508","article-title":"Training Deep Spiking Neural Networks Using Backpropagation","volume":"10","author":"Lee","year":"2016","journal-title":"Front. Neurosci."},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"129","DOI":"10.5573\/JSTS.2019.19.1.129","article-title":"A Low-power, Mixed-mode Neural Network Classifier for Robust Scene Classification","volume":"19","author":"Kyuho","year":"2019","journal-title":"J. Semicond. Technol. Sci."},{"key":"ref_6","unstructured":"Schuman, C.D., Potok, T.E., Patton, R.M., Birdwell, J.D., Dean, M.E., Rose, G.S., and Plank, J.S. (2021, January 25). A Survey of Neuromorphic Computing and Neural Networks in Hardware. Available online: http:\/\/arxiv.org\/abs\/1705.06963."},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"27","DOI":"10.1109\/85.238389","article-title":"First draft of a report on the EDVAC","volume":"15","year":"1993","journal-title":"IEEE Ann. Hist. Comput."},{"key":"ref_8","unstructured":"Kandel, E.R., Schwartz, J.H., and Jessell, T.M. (2012). Principles of Neural Science, McGraw-Hill, Health Professions Division. [5th ed.]."},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"28","DOI":"10.1109\/MSPEC.2017.7934228","article-title":"Special report: Can we copy the brain?\u2014The brain as computer","volume":"54","author":"Meier","year":"2017","journal-title":"IEEE Spectr."},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"76","DOI":"10.1038\/scientificamerican0591-76","article-title":"The silicon retina","volume":"Volume 264","author":"Mahowald","year":"1991","journal-title":"Scientific American"},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"40420","DOI":"10.1021\/acsami.7b11191","article-title":"Analog synaptic behavior of a silicon nitride memristor","volume":"9","author":"Kim","year":"2017","journal-title":"ACS Appl. Mater. Interfaces"},{"key":"ref_12","doi-asserted-by":"crossref","first-page":"2050073","DOI":"10.1142\/S0129065720500732","article-title":"Design and Implementation of a Spiking Neural Network with Integrate-and-Fire Neuron Model for Pattern Recognition","volume":"31","author":"Rashvand","year":"2021","journal-title":"Int. J. Neural Syst."},{"key":"ref_13","unstructured":"Mead, C. (1989). Anlaog VLSI and Neural Systems, Addison-Wesley. [1st ed.]."},{"key":"ref_14","doi-asserted-by":"crossref","unstructured":"Merolla, P., Arthur, J., Akopyan, F., Imam, N., Manohar, R., and Modha, D.S. (2011, January 19\u201321). A Digital Neurosynaptic Core Using Embedded Crossbar Memory with 45pJ per Spike in 45 nm. Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, USA.","DOI":"10.1109\/CICC.2011.6055294"},{"key":"ref_15","doi-asserted-by":"crossref","unstructured":"Islas, C., Padilla, P., and Prado, M.A. (2020). Information Processing in the Brain as Optimal Entropy Transport: A Theoretical Approach. Entropy, 22.","DOI":"10.3390\/e22111231"},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"1950003","DOI":"10.1142\/S0129065719500035","article-title":"How Far can Neural Correlations Reduce Uncertainty? Comparison of Information Transmission Rates for Markov and Bernoulli Processes","volume":"29","author":"Pregowska","year":"2019","journal-title":"Int. J. Neural Syst."},{"key":"ref_17","doi-asserted-by":"crossref","first-page":"3507","DOI":"10.3390\/e15093507","article-title":"The Measurement of Information Transmitted by a Neural Population: Promises and Challenges","volume":"15","author":"Crumiller","year":"2013","journal-title":"Entropy"},{"key":"ref_18","first-page":"145","article-title":"A 0.086-mm2 12.7-pJ\/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS","volume":"13","author":"Frenkel","year":"2019","journal-title":"IEEE Trans. Biomed. Circuits Syst."},{"key":"ref_19","doi-asserted-by":"crossref","unstructured":"Miyashita, D., Kousai, S., Suzuki, T., and Deguchi, J. (2016, January 7\u20139). Time-Domain Neural Network: A 48.5 TSOp\/s\/W neuromorphic chip optimized for deep learning and CMOS technology. Proceedings of the IEEE Asian SSC Conference, Toyama, Japan.","DOI":"10.1109\/ASSCC.2016.7844126"},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"3151","DOI":"10.1016\/j.cub.2015.10.063","article-title":"Energy-Efficient Information Transfer by Visual Pathway Synapses","volume":"25","author":"Harris","year":"2015","journal-title":"Curr. Biol."},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"4299","DOI":"10.1109\/TCSI.2018.2840718","article-title":"An Accelerated LIF Neuronal Network Array for a Large-Scale Mixed-Signal Neuromorphic Architecture","volume":"65","author":"Aamir","year":"2018","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_22","doi-asserted-by":"crossref","first-page":"118","DOI":"10.3389\/fnins.2011.00118","article-title":"Frontiers in Neuromorphic Engineering","volume":"5","author":"Indiveri","year":"2011","journal-title":"Front. Neurosci."},{"key":"ref_23","doi-asserted-by":"crossref","first-page":"2050","DOI":"10.1109\/JPROC.2011.2173089","article-title":"CMOS and memristor-based neural network design for position detection","volume":"100","author":"Ebong","year":"2012","journal-title":"Proc. IEEE"},{"key":"ref_24","doi-asserted-by":"crossref","first-page":"507","DOI":"10.1109\/TCT.1971.1083337","article-title":"Memristor-the missing circuit element","volume":"18","author":"Chua","year":"1971","journal-title":"IEEE Trans. Circuit Theory"},{"key":"ref_25","doi-asserted-by":"crossref","first-page":"2385","DOI":"10.1038\/s41467-018-04484-2","article-title":"Efficient and self-adaptive in-situ learning in multilayer memristor neural networks","volume":"9","author":"Li","year":"2018","journal-title":"Nat. Commun."},{"key":"ref_26","doi-asserted-by":"crossref","first-page":"699","DOI":"10.1109\/JPROC.2014.2313565","article-title":"Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations","volume":"102","author":"Benjamin","year":"2014","journal-title":"Proc. IEEE"},{"key":"ref_27","first-page":"21","article-title":"Compact spiking neural network chip design for image classification","volume":"28","author":"Park","year":"2020","journal-title":"J. RICIC"},{"key":"ref_28","doi-asserted-by":"crossref","unstructured":"Camu\u00f1as-Mesa, L.A., Linares-Barranco, B., and Serrano-Gotarredona, T. (2019). Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations. Materials, 12.","DOI":"10.3390\/ma12172745"},{"key":"ref_29","doi-asserted-by":"crossref","unstructured":"Ankit, A., Sengupta, A., Panda, P., and Roy, K. (2017, January 18\u201322). RESPARC: A Reconfigurable and Energy-Efficient Architecture with Memristive Crossbars for Deep SNN. Proceedings of the 54th ACM\/EDAC\/IEEE Design Automation Conference, Austin, TX, USA.","DOI":"10.1145\/3061639.3062311"},{"key":"ref_30","unstructured":"Jolivet, R., Rauch, A., L\u00fcscher, H.R., and Gerstner, W. (2005, January 5\u20138). Integrate-and-fire models with adaptation are good enough: Predicting spike times under random current injection. Proceedings of the NIPS 18, Vancouver, BC, Canada."},{"key":"ref_31","doi-asserted-by":"crossref","unstructured":"Gerstner, W., Kistler, W.M., Naud, R., and Paninski, L. (2014). Neuronal Dynamics, Cambridge University Press.","DOI":"10.1017\/CBO9781107447615"},{"key":"ref_32","doi-asserted-by":"crossref","first-page":"1569","DOI":"10.1109\/TNN.2003.820440","article-title":"Simple model of spiking neurons","volume":"14","author":"Izhikevich","year":"2003","journal-title":"IEEE Trans. Neural Netw."},{"key":"ref_33","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1016\/S0092-8240(05)80004-7","article-title":"A quantitative description of membrane current and its application to conduction and excitation in nerve","volume":"52","author":"Hodgkin","year":"1990","journal-title":"Bull. Math. Biol."},{"key":"ref_34","doi-asserted-by":"crossref","first-page":"99","DOI":"10.3389\/fncom.2015.00099","article-title":"Unsupervised learning of digit recognition using spike-timing-dependent plasticity","volume":"9","author":"Diehl","year":"2015","journal-title":"Front. Comput. Neurosci."},{"key":"ref_35","doi-asserted-by":"crossref","first-page":"2814","DOI":"10.1021\/acsnano.6b07894","article-title":"Pattern recognition using carbon nanotube synaptic transistors with an adjustable weight update protocol","volume":"11","author":"Kim","year":"2017","journal-title":"ACS Nano"},{"key":"ref_36","doi-asserted-by":"crossref","first-page":"4782","DOI":"10.1109\/TNNLS.2017.2778940","article-title":"High-performance mixed-signal neurocomputing with nanoscale floating-gate memory cell arrays","volume":"29","author":"Guo","year":"2018","journal-title":"IEEE Trans. Neural Netw. Learn. Syst."},{"key":"ref_37","doi-asserted-by":"crossref","first-page":"1220","DOI":"10.1109\/LED.2017.2731859","article-title":"Linking conductive filament properties and evolution to synaptic behavior of RRAM devices for neuromorphic applications","volume":"38","author":"Woo","year":"2017","journal-title":"IEEE Electron. Device Lett."},{"key":"ref_38","doi-asserted-by":"crossref","first-page":"630","DOI":"10.1109\/LED.2018.2809661","article-title":"Spiking Neural Network Using Synaptic Transistors and Neuron Circuits for Pattern Recognition with Noisy Images","volume":"39","author":"Kim","year":"2018","journal-title":"IEEE Electron. Device Lett."},{"key":"ref_39","unstructured":"O\u2019Connor, P., and Welling, M. (2021, January 20). Deep Spiking Networks. Available online: https:\/\/arxiv.org\/abs\/1602.08323."},{"key":"ref_40","doi-asserted-by":"crossref","first-page":"331","DOI":"10.3389\/fnins.2018.00331","article-title":"Spatio-Temporal Backpropagation for Training High-Performance Spiking Neural Networks","volume":"12","author":"Wu","year":"2018","journal-title":"Front. Neurosci."},{"key":"ref_41","doi-asserted-by":"crossref","unstructured":"Al-Hamid, A.A., and Kim, H. (2020). Optimization of Spiking Neural Networks Based on Binary Streamed Rate Coding. Electronics, 9.","DOI":"10.3390\/electronics9101599"},{"key":"ref_42","doi-asserted-by":"crossref","unstructured":"Asghar, M.S., Arslan, S., and Kim, H. (2020, January 21\u201324). Low Power Spiking Neural Network Circuit with Compact Synapse and Neuron Cells. Proceedings of the 2020 International SoC Design Conference, Yeosu, Korea.","DOI":"10.1109\/ISOCC50952.2020.9333105"},{"key":"ref_43","doi-asserted-by":"crossref","first-page":"8257","DOI":"10.1038\/s41598-017-07418-y","article-title":"Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET","volume":"7","author":"Dutta","year":"2017","journal-title":"Sci. Rep."},{"key":"ref_44","doi-asserted-by":"crossref","first-page":"211","DOI":"10.1109\/TNN.2005.860850","article-title":"A VLSI Array of Low-Power Spiking Neurons and Bistable Synapses with Spike-Timing Dependent Plasticity","volume":"17","author":"Indiveri","year":"2006","journal-title":"IEEE Trans. Neural Netw."},{"key":"ref_45","doi-asserted-by":"crossref","unstructured":"Tang, H., Kim, H., Cho, D., and Park, J. (2018, January 8\u201313). Spike Counts Based Low Complexity Learning with Binary Synapse. Proceedings of the 2018 International Joint Conference on Neural Networks, Rio de Janeiro, Brazil.","DOI":"10.1109\/IJCNN.2018.8489486"}],"container-title":["Sensors"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1424-8220\/21\/13\/4462\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T06:27:20Z","timestamp":1760164040000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1424-8220\/21\/13\/4462"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6,29]]},"references-count":45,"journal-issue":{"issue":"13","published-online":{"date-parts":[[2021,7]]}},"alternative-id":["s21134462"],"URL":"https:\/\/doi.org\/10.3390\/s21134462","relation":{},"ISSN":["1424-8220"],"issn-type":[{"value":"1424-8220","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,6,29]]}}}