{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T02:13:52Z","timestamp":1760235232263,"version":"build-2065373602"},"reference-count":17,"publisher":"MDPI AG","issue":"15","license":[{"start":{"date-parts":[[2021,7,31]],"date-time":"2021-07-31T00:00:00Z","timestamp":1627689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"publisher","award":["2018R1A6A1A03024003"],"award-info":[{"award-number":["2018R1A6A1A03024003"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100010418","name":"Institute for Information and Communications Technology Promotion","doi-asserted-by":"publisher","award":["IITP-2020-2020-0-01612"],"award-info":[{"award-number":["IITP-2020-2020-0-01612"]}],"id":[{"id":"10.13039\/501100010418","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003661","name":"Korea Institute for Advancement of Technology","doi-asserted-by":"publisher","award":["P0017011"],"award-info":[{"award-number":["P0017011"]}],"id":[{"id":"10.13039\/501100003661","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>A 3.0 Gsymbol\/s\/lane receiver is proposed herein to acquire near-grounded high-speed signals for the mobile industry processor interface (MIPI) C-PHY version 1.1 specification used for CMOS image sensor interfaces. Adaptive level-dependent equalization is also proposed to improve the signal integrity of the high-speed receivers receiving three-level signals. The proposed adaptive level-dependent equalizer (ALDE) is optimized by adjusting the duty cycle ratio of the clock recovered from the received data to 50%. A pre-determined data pattern transmitted from a MIPI C-PHY transmitter is established to perform the adaptive level-dependent equalization. The proposed MIPI C-PHY receiver with three data lanes is implemented using a 65 nm CMOS process with a 1.2 V supply voltage. The power consumption and area of each lane are 4.9 mW\/Gsymbol\/s\/lane and 0.097 mm2, respectively. The proposed ALDE improves the peak-to-peak time jitter of 12 ps and 34 ps, respectively, for the received data and the recovered clock at a symbol rate of 3 Gsymbol\/s\/lane. Additionally, the duty cycle ratio of the recovered clock is improved from 42.8% to 48.3%.<\/jats:p>","DOI":"10.3390\/s21155197","type":"journal-article","created":{"date-parts":[[2021,8,1]],"date-time":"2021-08-01T21:44:32Z","timestamp":1627854272000},"page":"5197","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["A 3.0 Gsymbol\/s\/lane MIPI C-PHY Receiver with Adaptive Level-Dependent Equalizer for Mobile CMOS Image Sensor"],"prefix":"10.3390","volume":"21","author":[{"given":"Seokwon","family":"Choi","sequence":"first","affiliation":[{"name":"OLED Design 1 Team, Silicon Mitus, Seongnam 13494, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Changmin","family":"Song","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Kumoh National Institute of Technology, Gumi 39177, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8680-9270","authenticated-orcid":false,"given":"Young-Chan","family":"Jang","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Kumoh National Institute of Technology, Gumi 39177, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2021,7,31]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Suzuki, A., Shimamura, N., Kainuma, T., Kawazu, N., Okada, C., Oka, T., Koiso, K., Masagaki, A., Yagasaki, Y., and Gonoi, S. (2015, January 22\u201326). A 1\/1.7-inch 20Mpixel Back-Illuminated Stacked CMOS Image Sensor for New Imaging Applications. Proceedings of the 2015 IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2015.7062950"},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Kim, S.-H., Shin, H., Jeong, Y., Lee, J.-H., Choi, J., and Chun, J.-H. (2018). A 12-Gb\/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems. Sensors, 18.","DOI":"10.3390\/s18082709"},{"key":"ref_3","doi-asserted-by":"crossref","unstructured":"Jung, Y.J., Venezia, V.C., Lee, S., Ai, C.Y., Zhu, Y., Yeung, K.W., Park, G., Choi, W., Lin, Z., and Yang, W.-Z. (2020, January 12\u201318). A 64M CMOS Image Sensor using 0.7um pixel with high FWC and switchable conversion. Proceedings of the 2020 IEEE International Electron Devices Meeting, San Francisco, CA, USA.","DOI":"10.1109\/IEDM13553.2020.9371889"},{"key":"ref_4","doi-asserted-by":"crossref","unstructured":"Park, J., Park, S., Cho, K., Lee, T., Lee, C., Kim, D., Lee, B., Kim, S., Ji, H.-C., and Im, D. (2021, January 13\u201322). 1\/2.74-inch 32Mpixel-Prototype CMOS Image Sensor with 0.64\u03bc m Unit Pixels Separated by Full-Depth Deep-Trench Isolation. Proceedings of the 2021 IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, USA.","DOI":"10.1109\/ISSCC42613.2021.9365751"},{"key":"ref_5","unstructured":"MIPI Alliance (2015, November 23). MIPI Alliance Specification for D-PHY, Version 2.0. November 2015. Available online: https:\/\/www.mipi.org\/specifications\/d-phy."},{"key":"ref_6","unstructured":"MIPI Alliance (2015, October 07). MIPI Alliance Specification for C-PHY, Version 1.1. October 2015. Available online: https:\/\/www.mipi.org\/specifications\/c-phy."},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Choi, W., Kim, T., Shim, J., Kim, H., Han, G., and Chae, Y. (2017, January 5\u20139). A 1V 7.8mW 15.6Gb\/s C-PHY transceiver using tri-level signaling for post-LPDDR4. Proceedings of the 2017 IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2017.7870431"},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"484","DOI":"10.1109\/TCE.2019.2942503","article-title":"A 20-Gb\/s Receiver Bridge Chip with Auto-Skew Calibration for MIPI D-PHY Interface","volume":"65","author":"Lee","year":"2019","journal-title":"IEEE Trans. Consumer Electron."},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"Kim, W., and Lee, M. (2021). A 92-\u03bcW\/Gbps Self-Biased SLVS Receiver for MIPI D-PHY Applications. IEEE Trans. Circuits Syst. II Express Briefs (Early Access).","DOI":"10.1109\/TCSII.2021.3074675"},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"69","DOI":"10.1109\/MSSC.2019.2910616","article-title":"The MIPI C-PHY Standard: A Generalized Multiconductor Signaling Scheme","volume":"11","author":"Lancheres","year":"2019","journal-title":"IEEE Solid-State Circuits Mag."},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"43","DOI":"10.1109\/JSSC.2018.2875092","article-title":"A 1.17pJ\/b 25Gb\/s\/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication in 16nm CMOS Using a Process- and Temperature-Adaptive Voltage Regulator","volume":"54","author":"Poulton","year":"2019","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_12","doi-asserted-by":"crossref","first-page":"978","DOI":"10.1109\/TVLSI.2014.2318733","article-title":"A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb\/s I\/O Links","volume":"23","author":"Chen","year":"2015","journal-title":"IEEE Trans. Very Large Integr. Syst."},{"key":"ref_13","first-page":"2672","article-title":"A 6.84 Gbps\/lane MIPI C-PHY Transceiver Bridge Chip with Level-Dependent Equalization","volume":"67","author":"Lee","year":"2020","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"ref_14","unstructured":"Choi, S. (2019). 3-GSymbol\/s\/lane MIPI C-PHY Receiver with Reduction of Channel Mismatch and Data-dependent Time Jitter. [Master\u2019s Thesis, Kumoh National Institute of Technology]."},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"681","DOI":"10.1109\/4.568834","article-title":"A 700-Mb\/s\/pin CMOS signaling interface using current integrating receivers","volume":"32","author":"Sidiropoulos","year":"1997","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"1063","DOI":"10.1109\/TCSII.2006.882186","article-title":"A Digital CMOS PWCL with Fixed-Delay Rising Edge and Digital Stability Control","volume":"53","author":"Jang","year":"2006","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"ref_17","doi-asserted-by":"crossref","first-page":"535","DOI":"10.1002\/jsid.916","article-title":"A 14-Gb\/s dual-mode receiver with MIPI D-PHY and C-PHY interfaces for mobile display drivers","volume":"28","author":"Kim","year":"2020","journal-title":"J. Soc. Inf. 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