{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T02:21:10Z","timestamp":1760235670436,"version":"build-2065373602"},"reference-count":20,"publisher":"MDPI AG","issue":"18","license":[{"start":{"date-parts":[[2021,9,10]],"date-time":"2021-09-10T00:00:00Z","timestamp":1631232000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>This paper presents a neural-network based nonlinear behavioral modelling of I\/O buffer that accounts for timing distortion introduced by nonlinear switching behavior of the predriver electrical circuit under power and ground supply voltage (PGSV) variations. Model structure and I\/O device characterization along with extraction procedure were described. The last stage of the I\/O buffer is modelled as nonlinear current-voltage (I-V) and capacitance voltage (C-V) functions capturing the nonlinear dynamic impedances of the pull-up and pull-down transistors. The mathematical model structure of the predriver was derived from the analysis of the large-signal electrical circuit switching behavior. Accordingly, a generic and surrogate multilayer neural network (NN) structure was considered in this work. Timing series data which reflects the nonlinear switching behavior of the multistage predriver\u2019s circuit PGSV variations, were used to train the NN model. The proposed model was implemented in the time-domain solver and validated against the reference transistor level (TL) model and the state-of-the-art input-output buffer information specification (IBIS) behavioral model under different scenarios. The analysis of jitter was performed using the eye diagrams plotted at different metrics values.<\/jats:p>","DOI":"10.3390\/s21186074","type":"journal-article","created":{"date-parts":[[2021,9,12]],"date-time":"2021-09-12T21:48:01Z","timestamp":1631483281000},"page":"6074","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Neural-Network Based Modeling of I\/O Buffer Predriver under Power\/Ground Supply Voltage Variations"],"prefix":"10.3390","volume":"21","author":[{"given":"Malek","family":"Souilem","sequence":"first","affiliation":[{"name":"\u00c9cole Nationale d\u2019Ing\u00e9nieurs de Sousse, Universit\u00e9 de Sousse, Sousse 4054, Tunisia"},{"name":"Laboratoire d\u2019Electroniques et Micro\u00e9lectroniques, Universit\u00e9 de Monastir, Monastir 5000, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jai Narayan","family":"Tripathi","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Indian Institute of Technology Jodhpur, Jodhpur 342037, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1081-2729","authenticated-orcid":false,"given":"Rui","family":"Melicio","sequence":"additional","affiliation":[{"name":"IDMEC, Instituto Superior T\u00e9cnico, Universidade de Lisboa, 1049-001 Lisboa, Portugal"},{"name":"ICT\u2014Instituto de Ci\u00eancias da Terra, Universidade de \u00c9vora, Rua Rom\u00e3o Ramalho 59, 7000-671 \u00c9vora, Portugal"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1777-2213","authenticated-orcid":false,"given":"Wael","family":"Dghais","sequence":"additional","affiliation":[{"name":"Institut Sup\u00e9rieur des Sciences Appliqu\u00e9es et de Technologie de Sousse, Universit\u00e9 de Sousse, Sousse 4003, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamdi","family":"Belgacem","sequence":"additional","affiliation":[{"name":"Laboratoire d\u2019Electroniques et Micro\u00e9lectroniques, Universit\u00e9 de Monastir, Monastir 5000, Tunisia"},{"name":"Institut Sup\u00e9rieur des Sciences Appliqu\u00e9es et de Technologie de Sousse, Universit\u00e9 de Sousse, Sousse 4003, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4589-5341","authenticated-orcid":false,"given":"Eduardo M. G.","family":"Rodrigues","sequence":"additional","affiliation":[{"name":"Management and Production Technologies of Northern Aveiro\u2014ESAN, Estrada do Cercal 449, Santiago de Riba-Ul, 3720-509 Oliveira de Azem\u00e9is, Portugal"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2021,9,10]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"392","DOI":"10.1109\/TEMC.2010.2045381","article-title":"Signal integrity design for high-speed digital circuits: Progress and directions","volume":"52","author":"Fan","year":"2010","journal-title":"IEEE Trans. Electromagn. Compat."},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Oh, D., and Shim, Y. (2014, January 4\u20138). Power integrity analysis for core timing models. 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