{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T02:24:29Z","timestamp":1760235869581,"version":"build-2065373602"},"reference-count":22,"publisher":"MDPI AG","issue":"19","license":[{"start":{"date-parts":[[2021,10,2]],"date-time":"2021-10-02T00:00:00Z","timestamp":1633132800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"Federal Ministry of Science &amp; Technology","award":["109-2221-E-324-028","110-2221-E-324-019","110-2221-E-224-052-MY2"],"award-info":[{"award-number":["109-2221-E-324-028","110-2221-E-324-019","110-2221-E-224-052-MY2"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows \u00d7 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 \u03bcW and 3.82 \u03bcW, while the average energy consumption is only 0.39 pJ.<\/jats:p>","DOI":"10.3390\/s21196591","type":"journal-article","created":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T21:37:49Z","timestamp":1633901869000},"page":"6591","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications"],"prefix":"10.3390","volume":"21","author":[{"given":"Ming-Hwa","family":"Sheu","sequence":"first","affiliation":[{"name":"Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu City 64002, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chang-Ming","family":"Tsai","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu City 64002, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ming-Yan","family":"Tsai","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu City 64002, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9828-0773","authenticated-orcid":false,"given":"Shih-Chang","family":"Hsia","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu City 64002, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6271-1022","authenticated-orcid":false,"given":"S. M. Salahuddin","family":"Morsalin","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu City 64002, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jin-Fa","family":"Lin","sequence":"additional","affiliation":[{"name":"Department of Information and Communication Engineering, Chaoyang University of Technology, Wufeng District, Taichung City 413310, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2021,10,2]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"2634","DOI":"10.1109\/TVLSI.2016.2520490","article-title":"Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell","volume":"24","author":"Ahmad","year":"2016","journal-title":"IEEE Trans. Very Large Scale Integr. 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