{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,15]],"date-time":"2025-10-15T10:31:11Z","timestamp":1760524271311,"version":"build-2065373602"},"reference-count":28,"publisher":"MDPI AG","issue":"20","license":[{"start":{"date-parts":[[2021,10,14]],"date-time":"2021-10-14T00:00:00Z","timestamp":1634169600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100014188","name":"Ministry of Science and ICT, South Korea","doi-asserted-by":"publisher","award":["2020R1A2C1012714"],"award-info":[{"award-number":["2020R1A2C1012714"]}],"id":[{"id":"10.13039\/501100014188","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003836","name":"IC Design Education Center","doi-asserted-by":"publisher","award":["."],"award-info":[{"award-number":["."]}],"id":[{"id":"10.13039\/501100003836","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002460","name":"Chung-Ang University","doi-asserted-by":"publisher","award":["GRS 2019"],"award-info":[{"award-number":["GRS 2019"]}],"id":[{"id":"10.13039\/501100002460","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N2). Between two possible sampling methods, sub-sampling and reference-sampling, the latter provides a relatively wide locking range, as the slower input reference signal is sampled with the faster VCO output signal. However, removal of FDIV makes the PLL not feasible to implement fractional-N operation based on varying divider ratios through random sequence generators, such as a Delta-Sigma-Modulator (DSM). To address the above design challenges, we propose a reference-sampling-based calibration-free fractional-N PLL (RSFPLL) with a phase-interpolator-linked sampling clock generator (PSCG). The proposed RSFPLL achieves fractional-N operations through phase-interpolator (PI)-based multi-phase generation instead of a typical frequency divider or digital-to-time converter (DTC). In addition, to alleviate the power burden arising from VCO-rated sampling, a flexible mask window generation method has been used that only passes a few sampling clocks near the point of interest. The prototype PLL system is designed with a 65 nm CMOS process with a chip size of 0.42 mm2. It achieves 322 fs rms jitter, \u2212240.7 dB figure-of-merit (FoM), and \u221244.06 dBc fractional spurs with 8.17 mW power consumption.<\/jats:p>","DOI":"10.3390\/s21206824","type":"journal-article","created":{"date-parts":[[2021,10,14]],"date-time":"2021-10-14T23:02:16Z","timestamp":1634252536000},"page":"6824","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator"],"prefix":"10.3390","volume":"21","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0287-4011","authenticated-orcid":false,"given":"Jae-Soub","family":"Han","sequence":"first","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea"}]},{"given":"Tae-Hyeok","family":"Eom","sequence":"additional","affiliation":[{"name":"Samsung Electronics, Hwaseong 18448, Korea"}]},{"given":"Seong-Wook","family":"Choi","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea"}]},{"given":"Kiho","family":"Seong","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea"}]},{"given":"Dong-Hyun","family":"Yoon","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore 639798, Singapore"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1779-1799","authenticated-orcid":false,"given":"Tony Tae-Hyong","family":"Kim","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore 639798, Singapore"}]},{"given":"Kwang-Hyun","family":"Baek","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea"}]},{"given":"Yong","family":"Shim","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea"}]}],"member":"1968","published-online":{"date-parts":[[2021,10,14]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"1617","DOI":"10.1109\/COMST.2016.2532458","article-title":"Next generation 5G wireless networks: A comprehensive survey","volume":"18","author":"Agiwal","year":"2016","journal-title":"IEEE Commun. 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