{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,7]],"date-time":"2026-03-07T18:12:14Z","timestamp":1772907134585,"version":"3.50.1"},"reference-count":51,"publisher":"MDPI AG","issue":"24","license":[{"start":{"date-parts":[[2021,12,14]],"date-time":"2021-12-14T00:00:00Z","timestamp":1639440000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>Nowadays, a large number of digital data are transmitted worldwide using wireless communications. Therefore, data security is a significant task in communication to prevent cybercrimes and avoid information loss. The Advanced Encryption Standard (AES) is a highly efficient secure mechanism that outperforms other symmetric key cryptographic algorithms using message secrecy. However, AES is efficient in terms of software and hardware implementation, and numerous modifications are done in the conventional AES architecture to improve the performance. This research article proposes a significant modification to the AES architecture\u2019s key expansion section to increase the speed of producing subkeys. The fork\u2013join model of key expansion (FJMKE) architecture is developed to improve the speed of the subkey generation process, whereas the hardware resources of AES are minimized by avoiding the frequent computation of secret keys. The AES-FJMKE architecture generates all of the required subkeys in less than half the time required by the conventional architecture. The proposed AES-FJMKE architecture is designed and simulated using the Xilinx ISE 5.1 software. The Field Programmable Gate Arrays (FPGAs) behaviour of the AES-FJMKE architecture is analysed by means of performance count for hardware resources, delay, and operating frequency. The existing AES architectures such as typical AES, AES-PNSG, AES-AT, AES-BE, ISAES, AES-RS, and AES-MPPRM are used to evaluate the efficiency of AES-FJMKE. The AES-FJMKE implemented using Spartan 6 FPGA used fewer slices (i.e., 76) than the AES-RS.<\/jats:p>","DOI":"10.3390\/s21248347","type":"journal-article","created":{"date-parts":[[2021,12,14]],"date-time":"2021-12-14T22:06:10Z","timestamp":1639519570000},"page":"8347","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":18,"title":["Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data"],"prefix":"10.3390","volume":"21","author":[{"given":"Thanikodi Manoj","family":"Kumar","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication Engineering, Karpagam Institute of Technology, Coimbatore 641105, Tamil Nadu, India"}]},{"given":"Kavitha Rani","family":"Balmuri","sequence":"additional","affiliation":[{"name":"Department of Information Technology, CMR Technical Campus, Hyderabad 501401, Telangana, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0651-3208","authenticated-orcid":false,"given":"Adam","family":"Marchewka","sequence":"additional","affiliation":[{"name":"Faculty of Telecommunications, Computer Science and Electrical Engineering, Bydgoszcz University of Science and Technology, 85-796 Bydgoszcz, Poland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3997-5070","authenticated-orcid":false,"given":"Parameshachari","family":"Bidare Divakarachari","sequence":"additional","affiliation":[{"name":"Department of Telecommunication Engineering, GSSS Institute of Engineering and Technology for Women, Mysuru 570016, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1119-0503","authenticated-orcid":false,"given":"Srinivas","family":"Konda","sequence":"additional","affiliation":[{"name":"Department of Computer Science Engineering, CMR Technical Campus, Kandlakoya, Hyderabad 501401, India"}]}],"member":"1968","published-online":{"date-parts":[[2021,12,14]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Visconti, P., Capoccia, S., Venere, E., Vel\u00e1zquez, R., and Fazio, R.D. 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