{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T16:53:39Z","timestamp":1777654419188,"version":"3.51.4"},"reference-count":31,"publisher":"MDPI AG","issue":"1","license":[{"start":{"date-parts":[[2021,12,22]],"date-time":"2021-12-22T00:00:00Z","timestamp":1640131200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>Aerospace equipages encounter potential radiation footprints through which soft errors occur in the memories onboard. Hence, robustness against radiation with reliability in memory cells is a crucial factor in aerospace electronic systems. This work proposes a novel Carbon nanotube field-effect transistor (CNTFET) in designing a robust memory cell to overcome these soft errors. Further, a petite driver circuit to test the SRAM cells which serve the purpose of precharge and sense amplifier, and has a reduction in threefold of transistor count is recommended. Additionally, analysis of robustness against radiation in varying memory cells is carried out using standard GPDK 90 nm, GPDK 45 nm, and 14 nm CNTFET. The reliability of memory cells depends on the critical charge of a device, and it is tested by striking an equivalent current charge of the cosmic ray\u2019s linear energy transfer (LET) level. Also, the robustness of the memory cell is tested against the variation in process, voltage and temperature. Though CNTFET surges with high power consumption, it exhibits better noise margin and depleted access time. GPDK 45 nm has an average of 40% increase in SNM and 93% reduction of power compared to the 14 nm CNTFET with 96% of surge in write access time. Thus, the conventional MOSFET\u2019s 45 nm node outperforms all the configurations in terms of static noise margin, power, and read delay which swaps with increased write access time.<\/jats:p>","DOI":"10.3390\/s22010033","type":"journal-article","created":{"date-parts":[[2021,12,23]],"date-time":"2021-12-23T02:02:57Z","timestamp":1640224977000},"page":"33","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":13,"title":["Design and Analysis of Soft Error Rate in FET\/CNTFET Based Radiation Hardened SRAM Cell"],"prefix":"10.3390","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9276-1936","authenticated-orcid":false,"given":"Bharathi Raj","family":"Muthu","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication Engineering, College of Engineering Guindy, Anna University, Chennai 600 025, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ewins Pon","family":"Pushpa","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, College of Engineering Guindy, Anna University, Chennai 600 025, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5235-2620","authenticated-orcid":false,"given":"Vaithiyanathan","family":"Dhandapani","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, National Institute of Technology, Delhi 110 040, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kamala","family":"Jayaraman","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, College of Engineering Guindy, Anna University, Chennai 600 025, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hemalatha","family":"Vasanthakumar","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, College of Engineering Guindy, Anna University, Chennai 600 025, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0154-7388","authenticated-orcid":false,"given":"Won-Chun","family":"Oh","sequence":"additional","affiliation":[{"name":"Department of Advanced Materials Science and Engineering, Hanseo University, Seosan-si 356-706, Chungnam, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Suresh","family":"Sagadevan","sequence":"additional","affiliation":[{"name":"Nanotechnology and Catalysis Research Centre, University of Malaya, Kuala Lumpur 50603, Malaysia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2021,12,22]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"310","DOI":"10.1038\/nature10676","article-title":"Multigate transistors as the future of classical metal\u2013oxide\u2013semiconductor field-effect transistors","volume":"479","author":"Ferain","year":"2011","journal-title":"Nature"},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1109\/TCSI.2011.2177004","article-title":"Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial","volume":"59","author":"Alioto","year":"2012","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"461","DOI":"10.1109\/23.490893","article-title":"Single-event effects in avionics","volume":"43","author":"Normand","year":"1996","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"3768","DOI":"10.1109\/TNS.2009.2032090","article-title":"A Soft Error Tolerant 10T SRAM Bit-Cell with Differential Read Capability","volume":"56","author":"Jahinuzzaman","year":"2009","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"2666","DOI":"10.1109\/TNS.2012.2218128","article-title":"Soft Error Susceptibilities of 22 nm Tri-Gate Devices","volume":"59","author":"Seifert","year":"2012","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"2266","DOI":"10.1109\/23.659045","article-title":"SEU critical charge and sensitive area in a submicron CMOS technology","volume":"44","author":"Detcheverry","year":"1997","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"113545","DOI":"10.1016\/j.microrel.2019.113545","article-title":"Reliable and high performance asymmetric FinFET SRAM cell using back-gate control","volume":"104","author":"Asli","year":"2020","journal-title":"Microelectron. Reliab."},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"153354","DOI":"10.1016\/j.aeue.2020.153354","article-title":"Sub-10 nm junctionless carbon nanotube field-effect transistors with improved performance","volume":"124","author":"Tamersit","year":"2020","journal-title":"AEU-Int. J. Electron. Commun."},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"499","DOI":"10.1038\/s41928-019-0330-2","article-title":"Carbon nanotube digital electronics","volume":"2","author":"Peng","year":"2019","journal-title":"Nat. Electron."},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"388","DOI":"10.1109\/TDMR.2016.2593590","article-title":"A Highly Reliable Memory Cell Design Combined with Layout-Level Approach to Tolerant Single-Event Upsets","volume":"16","author":"Qi","year":"2016","journal-title":"IEEE Trans. Device Mater. Reliab."},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"3040","DOI":"10.1109\/TNS.2015.2498919","article-title":"High Performance Low Power Pulse-Clocked TMR Circuits for Soft-Error Hardness","volume":"62","author":"Ramamurthy","year":"2015","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_12","doi-asserted-by":"crossref","first-page":"127","DOI":"10.1109\/TVLSI.2013.2238565","article-title":"Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code","volume":"22","author":"Guo","year":"2013","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"991","DOI":"10.1109\/TVLSI.2017.2788439","article-title":"Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications","volume":"26","author":"Guo","year":"2018","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"1593","DOI":"10.1109\/TVLSI.2016.2645282","article-title":"Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology","volume":"25","author":"Guo","year":"2017","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"key":"ref_15","doi-asserted-by":"crossref","unstructured":"Jung, I.-S., Kim, Y.-B., and Lombardi, F. (2012, January 5\u20138). A novel sort error hardened 10T SRAM cells for low voltage operation. Proceedings of the 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, ID, USA.","DOI":"10.1109\/MWSCAS.2012.6292120"},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"2647","DOI":"10.1016\/j.microrel.2015.09.011","article-title":"Heavy-ion irradiation study in SOI-based and bulk-based junctionless FinFETs using 3D-TCAD simulation","volume":"55","author":"Vinodhkumar","year":"2015","journal-title":"Microelectron. Reliab."},{"key":"ref_17","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1016\/j.microrel.2018.01.002","article-title":"Topological variation on sub-20 nm double-gate inversion and Junction-less-FinFET based 6T-SRAM circuits and its SEU radiation performance","volume":"82","author":"Nilamani","year":"2018","journal-title":"Microelectron. Reliab."},{"key":"ref_18","doi-asserted-by":"crossref","first-page":"113487","DOI":"10.1016\/j.microrel.2019.113487","article-title":"Impact of front-end wearout mechanisms on FinFET SRAM soft error rate","volume":"100\u2013101","author":"Zhang","year":"2019","journal-title":"Microelectron. Reliab."},{"key":"ref_19","first-page":"660","article-title":"Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology","volume":"76","author":"Artola","year":"2017","journal-title":"Microelectron. Reliab."},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"104942","DOI":"10.1016\/j.mejo.2020.104942","article-title":"Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node","volume":"107","author":"Vashishtha","year":"2021","journal-title":"Microelectron. J."},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"67","DOI":"10.1016\/j.aeue.2017.06.030","article-title":"Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM","volume":"80","author":"Singh","year":"2017","journal-title":"AEU-Int. J. Electron. Commun."},{"key":"ref_22","doi-asserted-by":"crossref","first-page":"152874","DOI":"10.1016\/j.aeue.2019.152874","article-title":"A robust and energy-efficient near-threshold SRAM cell utilizing ballistic carbon nanotube wrap-gate transistors","volume":"110","author":"Jooq","year":"2019","journal-title":"AEU-Int. J. Electron. Commun."},{"key":"ref_23","doi-asserted-by":"crossref","first-page":"5375","DOI":"10.1109\/TED.2019.2945533","article-title":"Carbon Nanotube-Based CMOS SRAM: 1 kbit 6T SRAM Arrays and 10T SRAM Cells","volume":"66","author":"Kanhaiya","year":"2019","journal-title":"IEEE Trans. Electron. Devices"},{"key":"ref_24","doi-asserted-by":"crossref","first-page":"3061","DOI":"10.1109\/TED.2015.2457453","article-title":"A compact virtual-source model for carbon nanotube FETs in the sub-10-nm regime\u2014Part I: Intrinsic elements","volume":"62","author":"Lee","year":"2015","journal-title":"IEEE Trans. Electron Devices"},{"key":"ref_25","doi-asserted-by":"crossref","unstructured":"Sinha, S., Yeric, G., Chandra, V., Cline, B., and Cao, Y. (2012, January 3\u20137). Exploring sub-20nm FinFET design with predictive technology models. Proceedings of the DAC Design Automation Conference, San Francisco, CA, USA.","DOI":"10.1145\/2228360.2228414"},{"key":"ref_26","doi-asserted-by":"crossref","first-page":"105","DOI":"10.1016\/j.mejo.2016.04.006","article-title":"ASAP7: A 7-nm finFET predictive process design kit","volume":"53","author":"Clark","year":"2016","journal-title":"Microelectron. J."},{"key":"ref_27","doi-asserted-by":"crossref","first-page":"758","DOI":"10.1021\/nl203701g","article-title":"Sub-10 nm Carbon Nanotube Transistor","volume":"12","author":"Franklin","year":"2012","journal-title":"Nano Lett."},{"key":"ref_28","doi-asserted-by":"crossref","first-page":"138","DOI":"10.1007\/s10825-017-1056-x","article-title":"Design and analysis of a gate-all-around CNTFET-based SRAM cell","volume":"17","author":"Kumar","year":"2018","journal-title":"J. Comput. Electron."},{"key":"ref_29","doi-asserted-by":"crossref","first-page":"967","DOI":"10.1109\/TCSI.2018.2872507","article-title":"Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications","volume":"66","author":"Jiang","year":"2018","journal-title":"IEEE Trans. Circuits Syst. I: Regul. Pap."},{"key":"ref_30","doi-asserted-by":"crossref","unstructured":"Sinha, A., Anand, N., Islam, A., and Sinha, A. (2014, January 10\u201311). Design metrics improvement of 10TSRAM cell using CNFET. Proceedings of the 2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), Kanyakumari, India.","DOI":"10.1109\/ICCICCT.2014.6992977"},{"key":"ref_31","doi-asserted-by":"crossref","unstructured":"Sun, L., Mathew, J., Shafik, R.A., Pradhan, D.K., and Li, Z. (2014, January 24\u201328). A low power and robust carbon nanotube 6T SRAM design with metallic tolerance. Proceedings of the 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany.","DOI":"10.7873\/DATE2014.125"}],"container-title":["Sensors"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1424-8220\/22\/1\/33\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T07:51:07Z","timestamp":1760169067000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1424-8220\/22\/1\/33"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12,22]]},"references-count":31,"journal-issue":{"issue":"1","published-online":{"date-parts":[[2022,1]]}},"alternative-id":["s22010033"],"URL":"https:\/\/doi.org\/10.3390\/s22010033","relation":{},"ISSN":["1424-8220"],"issn-type":[{"value":"1424-8220","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,12,22]]}}}