{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T18:44:27Z","timestamp":1761677067295,"version":"build-2065373602"},"reference-count":23,"publisher":"MDPI AG","issue":"2","license":[{"start":{"date-parts":[[2022,1,10]],"date-time":"2022-01-10T00:00:00Z","timestamp":1641772800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 \u03bcm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential structure charge pump (CP) are proposed respectively. In addition, a low noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider is realized. Finally, the phase locked loop (PLL) is realized by cascading each module. Measurement results show that the output signal frequency of the proposed CPPLL is 3.584 GHz\u20134.021 GHz, the phase noise at the frequency offset of 1 MHz is \u2212117.82 dBc\/Hz, and the maximum output power is 4.34 dBm. The chip area is 2701 \u03bcm \u00d7 3381 \u03bcm, and the power consumption is 181 mw.<\/jats:p>","DOI":"10.3390\/s22020504","type":"journal-article","created":{"date-parts":[[2022,1,10]],"date-time":"2022-01-10T22:03:13Z","timestamp":1641852193000},"page":"504","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process"],"prefix":"10.3390","volume":"22","author":[{"given":"Ranran","family":"Zhao","sequence":"first","affiliation":[{"name":"Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi\u2019an 710071, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuming","family":"Zhang","sequence":"additional","affiliation":[{"name":"Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi\u2019an 710071, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hongliang","family":"Lv","sequence":"additional","affiliation":[{"name":"Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi\u2019an 710071, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yue","family":"Wu","sequence":"additional","affiliation":[{"name":"Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi\u2019an 710071, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2022,1,10]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"1305","DOI":"10.1109\/JSSC.2010.2049458","article-title":"A 200 \u00b5A Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS","volume":"45","author":"Drago","year":"2010","journal-title":"IEEE J. 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