{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T00:33:36Z","timestamp":1760229216977,"version":"build-2065373602"},"reference-count":35,"publisher":"MDPI AG","issue":"11","license":[{"start":{"date-parts":[[2022,6,4]],"date-time":"2022-06-04T00:00:00Z","timestamp":1654300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"Chungnam National University"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an embedded dynamic random-access memory (eDRAM) macro for analog processing-in-memory (PIM). The proposed eDRAM cell consists of a two-transistor (2T) gain cell with a pseudo-static leakage compensation that maintains stored data without charge loss issue. Hence, the PS-GC can offer unlimited retention time in the same manner as static RAM (SRAM). Due to the extended retention time, bulky capacitors in conventional eDRAM are no longer needed, thereby, improving the area efficiency of eDRAM-based analog PIMs. The active leakage compensation of the PS-GC can effectively hold stored data even in a deep-submicron process that show significant leakage current. Therefore, the PS-GC can accelerate write-access time and read-access time without concern of increased leakage current. The proposed gain cell and its 64 \u00d7 64 eDRAM macro were implemented in a 28 nm CMOS process. The bitcell of the proposed gain cell has 0.79- and 0.58-times the area of those of 6T SRAM and 8T STAM, respectively. The post-layout simulation results demonstrate that the eDRAM maintains the pseudo-static operation with unlimited retention time successfully under wide range variations of process, voltage and temperature. At the operating frequency of 667 MHz, the eDRAM macro achieved an operating voltage range from 0.9 to 1.2 V and operating temperature range from \u221225 to 85 \u00b0C regardless of the process variation. The post-layout simulated write-access time and read-access time were below 0.3 ns at an operating temperature of 85 \u00b0C. The PS-GC consumes a static power of 2.2 nW\/bit at an operating temperature of 25 \u00b0C.<\/jats:p>","DOI":"10.3390\/s22114284","type":"journal-article","created":{"date-parts":[[2022,6,4]],"date-time":"2022-06-04T09:42:32Z","timestamp":1654335752000},"page":"4284","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes"],"prefix":"10.3390","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1926-595X","authenticated-orcid":false,"given":"Subin","family":"Kim","sequence":"first","affiliation":[{"name":"Department of Electronics Engineering, Chungnam National University, Daejeon 34134, Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6345-7903","authenticated-orcid":false,"given":"Jun-Eun","family":"Park","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering, Chungnam National University, Daejeon 34134, Korea"}]}],"member":"1968","published-online":{"date-parts":[[2022,6,4]]},"reference":[{"key":"ref_1","unstructured":"Zhang, J., Wang, Z., and Verma, N. (2016, January 15\u201317). A Machine-learning Classifier Implemented in a Standard 6T SRAM Array. Proceedings of the IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, USA."},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Yu, C., Yoo, T., Kim, T.T., Tshun Chuan, K.C., and Kim, B. (2020, January 22\u201325). A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read\/Write and 1-5bit Column ADC. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA.","DOI":"10.1109\/CICC48029.2020.9075883"},{"key":"ref_3","doi-asserted-by":"crossref","unstructured":"Chae, C., Kim, S., Choi, J., and Park, J.-E. (2021, January 6\u20139). A Multi-Bit In-Memory-Computing SRAM Macro Using Column-Wise Charge Redistribution for DNN Inference in Edge Computing Devices. Proceedings of the 18th International SoC Design Conference (ISOCC), Jeju Island, Korea.","DOI":"10.1109\/ISOCC53507.2021.9613934"},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"1888","DOI":"10.1109\/JSSC.2020.2992886","article-title":"C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism","volume":"55","author":"Jiang","year":"2020","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"1924","DOI":"10.1109\/JSSC.2021.3056447","article-title":"CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference","volume":"56","author":"Chen","year":"2021","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_6","doi-asserted-by":"crossref","unstructured":"Biswas, A., and Chandrakasan, A.P. (2018, January 11\u201315). Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications. Proceedings of the IEEE International Solid-State Circuits Conference-(ISSCC), San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2018.8310397"},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Su, J.-W., Chou, Y.-C., Liu, R., Liu, T.-W., Lu, P.-J., Wu, P.-C., Chung, Y.-L., Hung, L.-Y., Ren, J.-S., and Pan, T. (2021, January 13\u201322). 16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.","DOI":"10.1109\/ISSCC42613.2021.9365984"},{"key":"ref_8","doi-asserted-by":"crossref","unstructured":"Chen, W.-H., Li, K.-X., Lin, W.-Y., Hsu, K.-H., Li, P.-Y., Yang, C.-H., Xue, C.-X., Yang, E.-Y., Chen, Y.-K., and Chang, Y.-S. (2018, January 11\u201315). A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors. Proceedings of the IEEE International Solid-State Circuits Conference-(ISSCC), San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2018.8310400"},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"203","DOI":"10.1109\/JSSC.2019.2951363","article-title":"Embedded 1-Mb ReRAM-Based Computing-in-Memory Macro with Multibit Input and Weight for CNN-Based AI Edge Processors","volume":"55","author":"Xue","year":"2020","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_10","doi-asserted-by":"crossref","unstructured":"Khwa, W.-S., Chiu, Y.-C., Jhang, C.-J., Huang, S.-P., Lee, C.-Y., Wen, T.-H., Chang, F.-C., Yu, S.-M., Lee, T.-Y., and Chang, M.-F. (2022, January 20\u201326). A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5-65.0TOPS\/W for Tiny-Al Edge Devices. Proceedings of the IEEE International Solid-State Circuits Conference-(ISSCC), San Francisco, CA, USA.","DOI":"10.1109\/ISSCC42614.2022.9731670"},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"667","DOI":"10.1109\/TCSI.2020.3036209","article-title":"A Logic-Compatible eDRAM Compute-In-Memory with Embedded ADCs for Processing Neural Networks","volume":"68","author":"Yu","year":"2021","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_12","doi-asserted-by":"crossref","unstructured":"Xie, S., Ni, C., Sayal, A., Jain, P., Hamzaoglu, F., and Kulkarni, J.P. (2021, January 13\u201322). 16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing. Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.","DOI":"10.1109\/ISSCC42613.2021.9365932"},{"key":"ref_13","doi-asserted-by":"crossref","unstructured":"Raman, S.R.S., Xie, S., and Kulkarni, J.P. (2021, January 22\u201328). Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea.","DOI":"10.1109\/ISCAS51556.2021.9401798"},{"key":"ref_14","doi-asserted-by":"crossref","unstructured":"Hwang, M.-E., and Kwon, S. (2019). A 0.94 \u03bcW 611 KHz In-Situ Logic Operation in Embedded DRAM Memory Arrays in 90 nm CMOS. Electronics, 8.","DOI":"10.3390\/electronics8080865"},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"631","DOI":"10.1109\/JSSC.2008.2010811","article-title":"Fast Low Power eDRAM Hierarchical Differential Sense Amplifier","volume":"44","author":"Schuster","year":"2009","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_16","first-page":"1615","article-title":"A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation","volume":"68","author":"Sudarshan","year":"2021","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"ref_17","doi-asserted-by":"crossref","first-page":"222","DOI":"10.1109\/TCSI.2015.2512706","article-title":"Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs","volume":"63","author":"Edri","year":"2016","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_18","doi-asserted-by":"crossref","unstructured":"Golman, R., Giterman, R., and Teman, A. (2018, January 9\u201312). Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism. Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS), Bordeaux, France.","DOI":"10.1109\/ICECS.2018.8617861"},{"key":"ref_19","doi-asserted-by":"crossref","unstructured":"Maltabashi, O., Marinberg, H., Giterman, R., and Teman, A. (2018, January 27\u201330). A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy.","DOI":"10.1109\/ISCAS.2018.8351360"},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"174","DOI":"10.1109\/JSSC.2008.2007155","article-title":"2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes\/sec Bandwidth in a 65 nm Logic Process Technology","volume":"44","author":"Somasekhar","year":"2009","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"547","DOI":"10.1109\/JSSC.2011.2168729","article-title":"A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches","volume":"47","author":"Chun","year":"2012","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_22","doi-asserted-by":"crossref","first-page":"1495","DOI":"10.1109\/JSSC.2011.2128150","article-title":"A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches","volume":"46","author":"Chun","year":"2011","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_23","doi-asserted-by":"crossref","first-page":"1245","DOI":"10.1109\/TCSI.2017.2747087","article-title":"A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI","volume":"65","author":"Giterman","year":"2018","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_24","doi-asserted-by":"crossref","unstructured":"Narinx, J., Giterman, R., Bonetti, A., Frigerio, N., Aprile, C., Burg, A., and Leblebici, Y. (2019, January 4\u20136). A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications. Proceedings of the IEEE Asian Solid-State Circuits Conference (A-SSCC), Macau, China.","DOI":"10.1109\/A-SSCC47793.2019.9056985"},{"key":"ref_25","doi-asserted-by":"crossref","unstructured":"Saligram, R., Datta, S., and Raychowdhury, A. (2021, January 25\u201330). CryoMem: A 4K-300K 1.3 GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28 nm Logic Process for Cryogenic Applications. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA.","DOI":"10.1109\/CICC51472.2021.9431527"},{"key":"ref_26","first-page":"2042","article-title":"GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI","volume":"66","author":"Giterman","year":"2019","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"ref_27","doi-asserted-by":"crossref","first-page":"1207","DOI":"10.1109\/TCSI.2020.2971695","article-title":"Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space","volume":"67","author":"Giterman","year":"2020","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_28","doi-asserted-by":"crossref","first-page":"27641","DOI":"10.1109\/ACCESS.2019.2901738","article-title":"Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection","volume":"7","author":"Giterman","year":"2019","journal-title":"IEEE Access"},{"key":"ref_29","doi-asserted-by":"crossref","first-page":"2030","DOI":"10.1109\/TCSI.2013.2252652","article-title":"A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode","volume":"60","author":"Zhang","year":"2013","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_30","doi-asserted-by":"crossref","first-page":"358","DOI":"10.1109\/TVLSI.2015.2394459","article-title":"Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications","volume":"24","author":"Giterman","year":"2016","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_31","doi-asserted-by":"crossref","first-page":"2136","DOI":"10.1109\/JSSC.2018.2820145","article-title":"An 800-MHz Mixed-VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications","volume":"53","author":"Giterman","year":"2018","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_32","doi-asserted-by":"crossref","unstructured":"Teman, A., Meinerzhagen, P., Burg, A., and Fish, A. (2012, January 14\u201317). Review and Classification of Gain Cell eDRAM Implementations. Proceedings of the IEEE 27th Convention of Electrical and Electronics Engineers in Israel, Eilat, Israel.","DOI":"10.1109\/EEEI.2012.6377022"},{"key":"ref_33","doi-asserted-by":"crossref","first-page":"1319","DOI":"10.1109\/TVLSI.2021.3081043","article-title":"Gain-Cell Embedded DRAM Under Cryogenic Operation\u2014A First Study","volume":"29","author":"Greenblatt","year":"2021","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_34","doi-asserted-by":"crossref","first-page":"895","DOI":"10.1109\/JSSC.2004.842846","article-title":"SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction","volume":"40","author":"Zhang","year":"2005","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_35","doi-asserted-by":"crossref","first-page":"956","DOI":"10.1109\/JSSC.2007.917509","article-title":"An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches","volume":"43","author":"Chang","year":"2008","journal-title":"IEEE J. Solid-State Circuits"}],"container-title":["Sensors"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1424-8220\/22\/11\/4284\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,10]],"date-time":"2025-10-10T23:24:30Z","timestamp":1760138670000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1424-8220\/22\/11\/4284"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,4]]},"references-count":35,"journal-issue":{"issue":"11","published-online":{"date-parts":[[2022,6]]}},"alternative-id":["s22114284"],"URL":"https:\/\/doi.org\/10.3390\/s22114284","relation":{},"ISSN":["1424-8220"],"issn-type":[{"type":"electronic","value":"1424-8220"}],"subject":[],"published":{"date-parts":[[2022,6,4]]}}}