{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T02:13:27Z","timestamp":1760148807338,"version":"build-2065373602"},"reference-count":30,"publisher":"MDPI AG","issue":"15","license":[{"start":{"date-parts":[[2022,7,29]],"date-time":"2022-07-29T00:00:00Z","timestamp":1659052800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"the Ministry of Science and Technology, Taiwan","award":["110-2221-E-324-019","109AS-11.3.2-ST-a9"],"award-info":[{"award-number":["110-2221-E-324-019","109AS-11.3.2-ST-a9"]}]},{"name":"the Council of Agriculture, ROC","award":["110-2221-E-324-019","109AS-11.3.2-ST-a9"],"award-info":[{"award-number":["110-2221-E-324-019","109AS-11.3.2-ST-a9"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by using the pass transistor logic circuit scheme is proposed in this paper. Optimization measures lead to a new flip-flop design with better various performances such as speed, power, energy, and layout area. Based on post-layout simulation results using the TSMC CMOS 180 nm and 90 nm technologies, the proposed design achieves the conventional transmission-gate-based flip-flop design with a 53.6% reduction in power consumption and a 63.2% reduction in energy, with 12.5% input data switching activity. In order to further the performance parameters of the proposed design, a shift-register design has been realized. Experimental measurements at 0.5 V\/0.5 MHz show that this proposed design reduces power consumption by 47.3% while achieving a layout area reduction of 30.5% compared to the conventional design.<\/jats:p>","DOI":"10.3390\/s22155696","type":"journal-article","created":{"date-parts":[[2022,8,1]],"date-time":"2022-08-01T23:49:27Z","timestamp":1659397767000},"page":"5696","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design"],"prefix":"10.3390","volume":"22","author":[{"given":"Jin-Fa","family":"Lin","sequence":"first","affiliation":[{"name":"Department of Information and Communication Engineering, Chaoyang University of Technology, Wufeng District, Taichung City 413310, Taiwan"}]},{"given":"Zheng-Jie","family":"Hong","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, National Chung Hsing University, Taichung 40227, Taiwan"}]},{"given":"Jun-Ting","family":"Wu","sequence":"additional","affiliation":[{"name":"Department of Information and Communication Engineering, Chaoyang University of Technology, Wufeng District, Taichung City 413310, Taiwan"}]},{"given":"Xin-You","family":"Tung","sequence":"additional","affiliation":[{"name":"Department of Information and Communication Engineering, Chaoyang University of Technology, Wufeng District, Taichung City 413310, Taiwan"}]},{"given":"Cheng-Hsueh","family":"Yang","sequence":"additional","affiliation":[{"name":"Department of Information and Communication Engineering, Chaoyang University of Technology, Wufeng District, Taichung City 413310, Taiwan"}]},{"given":"Yu-Cheng","family":"Yen","sequence":"additional","affiliation":[{"name":"Department of Information and Communication Engineering, Chaoyang University of Technology, Wufeng District, Taichung City 413310, Taiwan"}]}],"member":"1968","published-online":{"date-parts":[[2022,7,29]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"23","DOI":"10.1109\/JETCAS.2013.2243031","article-title":"Synchronous logic and asynchronous-logic 8051 microcontroller cores for realizing the Internet of Things: A comparative study on dynamic voltage scaling and variation effects","volume":"3","author":"Chang","year":"2013","journal-title":"IEEE J. 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