{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T01:06:38Z","timestamp":1760231198263,"version":"build-2065373602"},"reference-count":23,"publisher":"MDPI AG","issue":"17","license":[{"start":{"date-parts":[[2022,8,30]],"date-time":"2022-08-30T00:00:00Z","timestamp":1661817600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"ICT (Institute of Earth Sciences) project","award":["UIDB\/04683\/2020","UIDB\/50022\/2020"],"award-info":[{"award-number":["UIDB\/04683\/2020","UIDB\/50022\/2020"]}]},{"name":"Foundation for Science and Technology (FCT)","award":["UIDB\/04683\/2020","UIDB\/50022\/2020"],"award-info":[{"award-number":["UIDB\/04683\/2020","UIDB\/50022\/2020"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>This paper presents the study of power\/ground (P\/G) supply-induced jitter (PGSIJ) on a cascaded inverter output buffer. The PGSIJ analysis covers the IO buffer transient simulation under P\/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct P\/G DC supply voltages at the pre-driver (i.e., VDD\/VSS) and last stage (i.e., VDDQ\/VSSQ). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P\/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input\u2013output buffer information specification (IBIS)-like model. Accordingly, the measured PGSIJ depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver\u2019s technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency\/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSIJ) induced by both the driver\u2019s IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions.<\/jats:p>","DOI":"10.3390\/s22176531","type":"journal-article","created":{"date-parts":[[2022,8,31]],"date-time":"2022-08-31T00:13:56Z","timestamp":1661904836000},"page":"6531","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Analysis of Pre-Driver and Last-Stage Power\u2014Ground-Induced Jitter at Different PVT Corners"],"prefix":"10.3390","volume":"22","author":[{"given":"Malek","family":"Souilem","sequence":"first","affiliation":[{"name":"\u00c9cole Nationale d\u2019Ing\u00e9nieurs de Sousse, Universit\u00e9 de Sousse, Sousse 4054, Tunisia"},{"name":"Laboratoire d\u2019Electroniques et Micro\u00e9lectroniques, Universit\u00e9 de Monastir, Monastir 5000, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1081-2729","authenticated-orcid":false,"given":"Rui","family":"Melicio","sequence":"additional","affiliation":[{"name":"IDMEC, Instituto Superior T\u00e9cnico, Universidade de Lisboa, 1049-001 Lisboa, Portugal"},{"name":"ICT\u2014Instituto de Ci\u00eancias da Terra, Universidade de \u00c9vora, Rua Rom\u00e3o Ramalho 59, 7000-671 \u00c9vora, Portugal"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1777-2213","authenticated-orcid":false,"given":"Wael","family":"Dghais","sequence":"additional","affiliation":[{"name":"Laboratoire d\u2019Electroniques et Micro\u00e9lectroniques, Universit\u00e9 de Monastir, Monastir 5000, Tunisia"},{"name":"Institut Sup\u00e9rieur des Sciences Appliqu\u00e9es et de Technologie de Sousse, Universit\u00e9 de Sousse, Sousse 4003, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamdi","family":"Belgacem","sequence":"additional","affiliation":[{"name":"Laboratoire d\u2019Electroniques et Micro\u00e9lectroniques, Universit\u00e9 de Monastir, Monastir 5000, Tunisia"},{"name":"Institut Sup\u00e9rieur des Sciences Appliqu\u00e9es et de Technologie de Sousse, Universit\u00e9 de Sousse, Sousse 4003, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4589-5341","authenticated-orcid":false,"given":"Eduardo","family":"Rodrigues","sequence":"additional","affiliation":[{"name":"INESC-ID, Sustainable Power Systems Group, Instituto Superior T\u00e9cnico, Universidade de Lisboa, Av. Rovisco Pais 1, 1049-001 Lisboa, Portugal"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2022,8,30]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"1240","DOI":"10.1109\/TCPMT.2011.2138704","article-title":"Accurate and scalable IO buffer macromodel based on surrogate modeling","volume":"1","author":"Zhu","year":"2011","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"458","DOI":"10.1109\/TDMR.2011.2160062","article-title":"Surrogate-modelbased analysis of analog circuits-part II: Reliability analysis","volume":"11","author":"Yelten","year":"2011","journal-title":"IEEE Trans. Device Mater. Reliab."},{"key":"ref_3","doi-asserted-by":"crossref","unstructured":"Song, K., Kim, J., Kim, H., Lee, S., Ahn, J., Brito, A., Kim, H., Park, M., and Ahn, S. (2021). Modeling, Verification, and Signal Integrity Analysis of High-Speed Signaling Channel with Tabbed Routing in High Performance Computing Server Board. Electronics, 10.","DOI":"10.3390\/electronics10131590"},{"key":"ref_4","doi-asserted-by":"crossref","unstructured":"Satheesh, S.M., and Salman, E. (2012, January 12\u201314). Design space exploration for robust power delivery in TSV based 3-D systems-on-chip. Proceedings of the 2012 IEEE International SOC Conference, Niagara Falls, NY, USA.","DOI":"10.1109\/SOCC.2012.6398327"},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"511","DOI":"10.1109\/TCPMT.2018.2872608","article-title":"A Review on Power Supply Induced Jitter","volume":"3","author":"Tripathi","year":"2019","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"468","DOI":"10.1109\/TEMC.2017.2725270","article-title":"Analytic Calculation of Jitter Induced by Power and Ground Noise Based on IBIS I\/V Curve","volume":"60","author":"Chu","year":"2018","journal-title":"IEEE Trans. Electromagn. Compat."},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Park, E., Kim, J., Kim, H., and Shon, K. (2014, January 4\u20138). Analytical jitter estimation of two-stage output buffers with supply voltage fluctuations. Proceedings of the 2014 IEEE International Symposium on Electromagnetic Compatibility (EMC), Raleigh, NC, USA.","DOI":"10.1109\/ISEMC.2014.6898945"},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"15","DOI":"10.1109\/TADVP.2004.825475","article-title":"M\/spl pi\/log, macromodeling via parametric identification of logic gates","volume":"27","author":"Stievano","year":"2004","journal-title":"IEEE Trans. Adv. Packag."},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"Souilem, M., Tripathi, J.N., Dghais, W., and Belgacem, H. (2019, January 6\u20139). I\/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO). Proceedings of the 2019 IFIP\/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), Cuzco, Peru.","DOI":"10.1109\/VLSI-SoC.2019.8920351"},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"711","DOI":"10.1109\/TADVP.2008.2004995","article-title":"Improving Behavioral IO Buffer Modeling Based on IBIS","volume":"31","author":"Varma","year":"2008","journal-title":"IEEE Trans. Adv. Packag."},{"key":"ref_11","doi-asserted-by":"crossref","unstructured":"Lan, H., Schmitt, R., and Yuan, C. (2008, January 2). Prediction and measurement of supply noise induced jitter in high-speed I\/O interfaces. Proceedings of the DesignCon, San Francisco, CA, USA.","DOI":"10.1109\/ISQED.2008.4479817"},{"key":"ref_12","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1155\/2018\/1356538","article-title":"Power Supply and Temperature Aware I\/O Buffer Model for Signal-Power Integrity Simulation","volume":"2018","author":"Dghais","year":"2018","journal-title":"Math. Probl. Eng."},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"233","DOI":"10.1109\/TVLSI.2019.2936815","article-title":"Behavioral Modeling of Tunable I\/O Drivers With Preemphasis Including Power Supply Noise","volume":"28","author":"Yu","year":"2020","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_14","unstructured":"(2022, August 23). I\/O Buffer Information Specification Version 7.0. Available online: https:\/\/ibis.org\/ver7.0\/ver7_0.pdf."},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"447","DOI":"10.1109\/TCPMT.2015.2512911","article-title":"New Multiport I\/O Model for Power-Aware Signal Integrity Analysis","volume":"6","author":"Dghais","year":"2016","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_16","doi-asserted-by":"crossref","unstructured":"Souilem, M., Tripathi, J.N., Melicio, R., Dghais, W., Belgacem, H., and Rodrigues, E.M.G. (2021). Neural-Network Based Modeling of I\/O Buffer Predriver under Power\/Ground Supply Voltage Variations. Sensors, 21.","DOI":"10.3390\/s21186074"},{"key":"ref_17","doi-asserted-by":"crossref","unstructured":"Schmitt, R., Lan, H., Madden, C., and Yuan, C. (2007). Investigating the impact of supply noise on the jitter in gigabit I\/O interfaces. 2007 IEEE Electrical Performance of Electronic Packaging, IEEE.","DOI":"10.1109\/EPEP.2007.4387157"},{"key":"ref_18","doi-asserted-by":"crossref","unstructured":"Shim, Y., Oh, D., Thim Khor, C., Dhavale, B., Chandra, S., Chow, D., Ding, W., Chand, K., Aflaki, A., and Sarmiento, M. (2013, January 28\u201331). System level clock jitter modeling for DDR systems. Proceedings of the 2013 IEEE 63rd Electronic Components and Technology Conference, Las Vegas, NV, USA.","DOI":"10.1109\/ECTC.2013.6575749"},{"key":"ref_19","unstructured":"Kang, H.S., Chen, G., Hashemi, A., Choo, W.S., Greenhill, D., and Beyene, W. (, January January). Simulation and measurement correlation of power supply noise induced jitter for core and digital IP blocks. Proceedings of the Proc. Des. Conf., CA, USA. Available online: https:\/\/www.researchgate.net\/publication\/339149584_Simulation_and_measurement_correlation_of_power_supply_noise_induced_jitter_for_core_and_digital_IP_blocks."},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"1349","DOI":"10.1109\/TEMC.2016.2574720","article-title":"System Level Modeling of Timing Margin Loss Due to Dynamic Supply Noise for High-Speed Clock Forwarding Interface","volume":"58","author":"Shim","year":"2016","journal-title":"IEEE Trans. Electromagn. Compat."},{"key":"ref_21","unstructured":"Shenoy, P., and Nowakowski, R. (2016). Power delivery for space-constrained applications. White Paper, Texas Instruments."},{"key":"ref_22","doi-asserted-by":"crossref","unstructured":"Kim, H., Fan, J., and Hwang, C. (2017, January 7\u201311). Modeling of power supply induced jitter (PSIJ) transfer function at inverter chains. Proceedings of the 2017 IEEE International Symposium on Electromagnetic Compatibility and Signal\/Power Integrity (EMCSI), Washington, DC, USA.","DOI":"10.1109\/ISEMC.2017.8077937"},{"key":"ref_23","doi-asserted-by":"crossref","first-page":"1491","DOI":"10.1109\/TEMC.2017.2764867","article-title":"Precise Analytical Model of Power Supply Induced Jitter Transfer Function at Inverter Chains","volume":"60","author":"Kim","year":"2017","journal-title":"IEEE Trans. Electromagn. Compat."}],"container-title":["Sensors"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1424-8220\/22\/17\/6531\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T00:20:12Z","timestamp":1760142012000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1424-8220\/22\/17\/6531"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,8,30]]},"references-count":23,"journal-issue":{"issue":"17","published-online":{"date-parts":[[2022,9]]}},"alternative-id":["s22176531"],"URL":"https:\/\/doi.org\/10.3390\/s22176531","relation":{},"ISSN":["1424-8220"],"issn-type":[{"type":"electronic","value":"1424-8220"}],"subject":[],"published":{"date-parts":[[2022,8,30]]}}}