{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,8]],"date-time":"2025-11-08T13:38:58Z","timestamp":1762609138056,"version":"build-2065373602"},"reference-count":15,"publisher":"MDPI AG","issue":"4","license":[{"start":{"date-parts":[[2023,2,7]],"date-time":"2023-02-07T00:00:00Z","timestamp":1675728000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"Regional Innovation Strategy (RIS)","award":["2021RIS-004","IITP-2023-RS-2022-00156212"],"award-info":[{"award-number":["2021RIS-004","IITP-2023-RS-2022-00156212"]}]},{"name":"Ministry of Education(MOE)","award":["2021RIS-004","IITP-2023-RS-2022-00156212"],"award-info":[{"award-number":["2021RIS-004","IITP-2023-RS-2022-00156212"]}]},{"name":"MSIT (Ministry of Science and ICT), Korea","award":["2021RIS-004","IITP-2023-RS-2022-00156212"],"award-info":[{"award-number":["2021RIS-004","IITP-2023-RS-2022-00156212"]}]},{"name":"IITP (Institute of Information &amp; Communications Technology Planning &amp; Evaluation)","award":["2021RIS-004","IITP-2023-RS-2022-00156212"],"award-info":[{"award-number":["2021RIS-004","IITP-2023-RS-2022-00156212"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>This paper presents an ultra-low-power voltage reference designed in 180 nm CMOS technology. To achieve near-zero line sensitivity, a two-transistor (2-T) voltage reference is biased with a current source to cancel the drain-induced barrier-lowering (DIBL) effect of the 2-T core, thus improving the line sensitivity. This compensation circuit achieves a Monte-Carlo-simulated line sensitivity of 0.035 %\/V in a supply range of 0.6 to 1.8 V, while generating a reference voltage of 307.8 mV, with 21.4 pW power consumption. The simulated power supply rejection ratio (PSRR) is \u221254 dB at 100 Hz. It also achieves a temperature coefficient of 24.8 ppm\/\u00b0C in a temperature range of \u221220 to 80 \u00b0C, with a projected area of 0.003 mm2.<\/jats:p>","DOI":"10.3390\/s23041862","type":"journal-article","created":{"date-parts":[[2023,2,8]],"date-time":"2023-02-08T02:04:16Z","timestamp":1675821856000},"page":"1862","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["A 21.4 pW Subthreshold Voltage Reference with 0.020 %\/V Line Sensitivity Using DIBL Compensation"],"prefix":"10.3390","volume":"23","author":[{"given":"Louis","family":"Colbach","sequence":"first","affiliation":[{"name":"Department of Information Technology and Electrical Engineering, ETH Zurich, 8092 Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Taekwang","family":"Jang","sequence":"additional","affiliation":[{"name":"Department of Information Technology and Electrical Engineering, ETH Zurich, 8092 Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4319-6619","authenticated-orcid":false,"given":"Youngwoo","family":"Ji","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Hanbat National University, Daejeon 34158, Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2023,2,7]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"267","DOI":"10.1109\/JSSC.2020.3033467","article-title":"A 1.16-V 5.8-to-13.5-ppm\/\u00b0C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers","volume":"56","author":"Chen","year":"2021","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"1197","DOI":"10.1109\/JSSC.2020.3044165","article-title":"A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3\u03c3 Inaccuracy of +0.02%, \u22120.12% for Battery-Monitoring Applications","volume":"56","author":"Boo","year":"2021","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"2902","DOI":"10.1109\/JSSC.2021.3093583","article-title":"A Single BJT Bandgap Reference with Frequency Compensation Exploiting Mirror Pole","volume":"56","author":"Kim","year":"2021","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"2534","DOI":"10.1109\/JSSC.2012.2206683","article-title":"A PorTable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V","volume":"47","author":"Seok","year":"2012","journal-title":"IEEE J. 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Pap."},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"1443","DOI":"10.1109\/JSSC.2017.2654326","article-title":"A Subthreshold Voltage Reference With Scalable Output Voltage for Low-Power IoT Systems","volume":"52","author":"Lee","year":"2017","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"3790","DOI":"10.1109\/TCSI.2018.2859341","article-title":"A 0.12\u20130.4 V, Versatile 3-Transistor CMOS Voltage Reference for Ultra-Low Power Systems","volume":"65","author":"Cordova","year":"2018","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_10","unstructured":"Qing, D., Kaiyuan, Y., Blaauw, D., and Sylvester, D. (2016, January 15\u201317). A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems. 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