{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,21]],"date-time":"2026-04-21T14:58:16Z","timestamp":1776783496209,"version":"3.51.2"},"reference-count":71,"publisher":"MDPI AG","issue":"6","license":[{"start":{"date-parts":[[2023,3,9]],"date-time":"2023-03-09T00:00:00Z","timestamp":1678320000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"Infineon Technologies Austria"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>Analog mixed-signal (AMS) verification is one of the essential tasks in the development process of modern systems-on-chip (SoC). Most parts of the AMS verification flow are already automated, except for stimuli generation, which has been performed manually. It is thus challenging and time-consuming. Hence, automation is a necessity. To generate stimuli, subcircuits or subblocks of a given analog circuit module should be identified\/classified. However, there currently needs to be a reliable industrial tool that can automatically identify\/classify analog sub-circuits (eventually in the frame of a circuit design process) or automatically classify a given analog circuit at hand. Besides verification, several other processes would profit enormously from the availability of a robust and reliable automated classification model for analog circuit modules (which may belong to different levels). This paper presents how to use a Graph Convolutional Network (GCN) model and proposes a novel data augmentation strategy to automatically classify analog circuits of a given level. Eventually, it can be upscaled or integrated within a more complex functional module (for a structure recognition of complex analog circuits), targeting the identification of subcircuits within a more complex analog circuit module. An integrated novel data augmentation technique is particularly crucial due to the harsh reality of the availability of generally only a relatively limited dataset of analog circuits\u2019 schematics (i.e., sample architectures) in practical settings. Through a comprehensive ontology, we first introduce a graph representation framework of the circuits\u2019 schematics, which consists of converting the circuit\u2019s related netlists into graphs. Then, we use a robust classifier consisting of a GCN processor to determine the label corresponding to the given input analog circuit\u2019s schematics. Furthermore, the classification performance is improved and robust by involving a novel data augmentation technique. The classification accuracy was enhanced from 48.2% to 76.6% using feature matrix augmentation, and from 72% to 92% using Dataset Augmentation by Flipping. A 100% accuracy was achieved after applying either multi-Stage augmentation or Hyperphysical Augmentation. Overall, extensive tests of the concept were developed to demonstrate high accuracy for the analog circuit\u2019s classification endeavor. This is solid support for a future up-scaling towards an automated analog circuits\u2019 structure detection, which is one of the prerequisites not only for the stimuli generation in the frame of analog mixed-signal verification but also for other critical endeavors related to the engineering of AMS circuits.<\/jats:p>","DOI":"10.3390\/s23062989","type":"journal-article","created":{"date-parts":[[2023,3,10]],"date-time":"2023-03-10T02:05:54Z","timestamp":1678413954000},"page":"2989","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":9,"title":["A Robust Automated Analog Circuits Classification Involving a Graph Neural Network and a Novel Data Augmentation Strategy"],"prefix":"10.3390","volume":"23","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1597-6113","authenticated-orcid":false,"given":"Ali","family":"Deeb","sequence":"first","affiliation":[{"name":"Institute for Smart Systems Technologies, Universitaet Klagenfurt, 9020 Klagenfurt, Austria"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abdalrahman","family":"Ibrahim","sequence":"additional","affiliation":[{"name":"Infineon Technologies Austria, 9500 Villach, Austria"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1573-2450","authenticated-orcid":false,"given":"Mohamed","family":"Salem","sequence":"additional","affiliation":[{"name":"Infineon Technologies Austria, 9500 Villach, Austria"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joachim","family":"Pichler","sequence":"additional","affiliation":[{"name":"Infineon Technologies Austria, 9500 Villach, Austria"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sergii","family":"Tkachov","sequence":"additional","affiliation":[{"name":"Infineon Technologies Austria, 9500 Villach, Austria"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anjeza","family":"Karaj","sequence":"additional","affiliation":[{"name":"Infineon Technologies Austria, 9500 Villach, Austria"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1239-9261","authenticated-orcid":false,"given":"Fadi","family":"Al Machot","sequence":"additional","affiliation":[{"name":"Faculty of Science and Technology, Norwegian University of Life Sciences (NMBU), 1430 \u00c5s, Norway"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0773-9476","authenticated-orcid":false,"given":"Kyamakya","family":"Kyandoghere","sequence":"additional","affiliation":[{"name":"Institute for Smart Systems Technologies, Universitaet Klagenfurt, 9020 Klagenfurt, Austria"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2023,3,9]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"180","DOI":"10.1109\/TCAD.2010.2097172","article-title":"Comprehensive generation of hierarchical placement rules for analog integrated circuits","volume":"30","author":"Eick","year":"2011","journal-title":"IEEE Trans. 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