{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T02:26:34Z","timestamp":1760149594307,"version":"build-2065373602"},"reference-count":34,"publisher":"MDPI AG","issue":"17","license":[{"start":{"date-parts":[[2023,8,29]],"date-time":"2023-08-29T00:00:00Z","timestamp":1693267200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"National Natural Science Foundation of China","award":["62274068"],"award-info":[{"award-number":["62274068"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>This paper presents an innovative approach for predicting timing errors tailored to near-\/sub-threshold operations, addressing the energy-efficient requirements of digital circuits in applications, such as IoT devices and wearables. The method involves assessing deep path activity within an adjustable window prior to the root clock\u2019s rising edge. By dynamically adapting the prediction window and supply voltage based on error detection outcomes, the approach effectively mitigates false predictions\u2014an essential concern in low-voltage prediction techniques. The efficacy of this strategy is demonstrated through its implementation in a near-\/sub-threshold 32-bit microprocessor system. The approach incurs only a modest 6.84% area overhead attributed to well-engineered lightweight design methodologies. Furthermore, with the integration of clock gating, the system functions seamlessly across a voltage range of 0.4 V\u20131.2 V (5\u2013100 MHz), effectively catering to adaptive energy efficiency. Empirical results highlight the potential of the proposed strategy, achieving a significant 46.95% energy reduction at the Minimum Energy Point (MEP, 15 MHz) compared to signoff margins. Additionally, a 19.75% energy decrease is observed compared to the zero-margin operation, demonstrating successful realization of negative margins.<\/jats:p>","DOI":"10.3390\/s23177498","type":"journal-article","created":{"date-parts":[[2023,8,29]],"date-time":"2023-08-29T08:59:05Z","timestamp":1693299545000},"page":"7498","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller"],"prefix":"10.3390","volume":"23","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-9806-3559","authenticated-orcid":false,"given":"Run-Ze","family":"Yu","sequence":"first","affiliation":[{"name":"School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, China"}]},{"given":"Zhen-Hao","family":"Li","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, China"}]},{"given":"Xi","family":"Deng","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, China"}]},{"given":"Zheng-Lin","family":"Liu","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, China"}]}],"member":"1968","published-online":{"date-parts":[[2023,8,29]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Kim, J.K., Knag, P., Chen, T., and Zhang, Z. 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