{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T02:41:07Z","timestamp":1760150467192,"version":"build-2065373602"},"reference-count":41,"publisher":"MDPI AG","issue":"23","license":[{"start":{"date-parts":[[2023,11,22]],"date-time":"2023-11-22T00:00:00Z","timestamp":1700611200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"National Research Foundation of Korea"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>This paper introduces an n-type pseudo-static gain cell (PS-nGC) embedded within dynamic random-access memory (eDRAM) for high-speed processing-in-memory (PIM) applications. The PS-nGC leverages a two-transistor (2T) gain cell and employs an n-type pseudo-static leakage compensation (n-type PSLC) circuit to significantly extend the eDRAM\u2019s retention time. The implementation of a homogeneous NMOS-based 2T gain cell not only reduces write access times but also benefits from a boosted write wordline technique. In a comparison with the previous pseudo-static gain cell design, the proposed PS-nGC exhibits improvements in write and read access times, achieving 3.27 times and 1.81 times reductions in write access time and read access time, respectively. Furthermore, the PS-nGC demonstrates versatility by accommodating a wide supply voltage range, spanning from 0.7 to 1.2 V, while maintaining an operating frequency of 667 MHz. Fabricated using a 28 nm complementary metal oxide semiconductor (CMOS) process, the prototype features an efficient active area, occupying a mere 0.284 \u00b5m2 per bitcell for the 4 kb eDRAM macro. Under various operational conditions, including different processes, voltages, and temperatures, the proposed PS-nGC of eDRAM consistently provides speedy and reliable read and write operations.<\/jats:p>","DOI":"10.3390\/s23239329","type":"journal-article","created":{"date-parts":[[2023,11,22]],"date-time":"2023-11-22T10:41:51Z","timestamp":1700649711000},"page":"9329","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["An N-Type Pseudo-Static eDRAM Macro with Reduced Access Time for High-Speed Processing-in-Memory in Intelligent Sensor Hub Applications"],"prefix":"10.3390","volume":"23","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1926-595X","authenticated-orcid":false,"given":"Subin","family":"Kim","sequence":"first","affiliation":[{"name":"LX Semicon, Seoul 06763, Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ingu","family":"Jeong","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6345-7903","authenticated-orcid":false,"given":"Jun-Eun","family":"Park","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Republic of Korea"},{"name":"Department of Electronics Engineering, Chungnam National University, Daejeon 34134, Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2023,11,22]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"3466","DOI":"10.1109\/JSSC.2022.3162602","article-title":"A 65-nm 8T SRAM Compute-in-Memory Macro with Column ADCs for Processing Neural Networks","volume":"57","author":"Yu","year":"2022","journal-title":"IEEE J. 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