{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T16:20:36Z","timestamp":1775665236110,"version":"3.50.1"},"reference-count":42,"publisher":"MDPI AG","issue":"15","license":[{"start":{"date-parts":[[2024,7,23]],"date-time":"2024-07-23T00:00:00Z","timestamp":1721692800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"Datalogic IP-Tech"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>Binary neural networks (BNNs) can substantially accelerate a neural network\u2019s inference time by substituting its costly floating-point arithmetic with bit-wise operations. Nevertheless, state-of-the-art approaches reduce the efficiency of the data flow in the BNN layers by introducing intermediate conversions from 1 to 16\/32 bits. We propose a novel training scheme, denoted as BNN-Clip, that can increase the parallelism and data flow of the BNN pipeline; specifically, we introduce a clipping block that reduces the data width from 32 bits to 8. Furthermore, we decrease the internal accumulator size of a binary layer, usually kept using 32 bits to prevent data overflow, with no accuracy loss. Moreover, we propose an optimization of the batch normalization layer that reduces latency and simplifies deployment. Finally, we present an optimized implementation of the binary direct convolution for ARM NEON instruction sets. Our experiments show a consistent inference latency speed-up (up to 1.3 and 2.4\u00d7 compared to two state-of-the-art BNN frameworks) while reaching an accuracy comparable with state-of-the-art approaches on datasets like CIFAR-10, SVHN, and ImageNet.<\/jats:p>","DOI":"10.3390\/s24154780","type":"journal-article","created":{"date-parts":[[2024,7,24]],"date-time":"2024-07-24T10:46:20Z","timestamp":1721817980000},"page":"4780","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Optimizing Data Flow in Binary Neural Networks"],"prefix":"10.3390","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4634-2044","authenticated-orcid":false,"given":"Lorenzo","family":"Vorabbi","sequence":"first","affiliation":[{"name":"Datalogic Labs, Via San Vitalino 12, 40012 Bologna, BO, Italy"},{"name":"Department of Computer Science and Engineering (DISI), University of Bologna, Cesena Campus, Via dell\u2019 Universit\u00e0 50, 47521 Cesena, FC, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6329-6756","authenticated-orcid":false,"given":"Davide","family":"Maltoni","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering (DISI), University of Bologna, Cesena Campus, Via dell\u2019 Universit\u00e0 50, 47521 Cesena, FC, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefano","family":"Santi","sequence":"additional","affiliation":[{"name":"Datalogic Labs, Via San Vitalino 12, 40012 Bologna, BO, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2024,7,23]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"211","DOI":"10.1007\/s11263-015-0816-y","article-title":"ImageNet Large Scale Visual Recognition Challenge","volume":"115","author":"Russakovsky","year":"2015","journal-title":"Int. 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