{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,22]],"date-time":"2026-04-22T13:38:36Z","timestamp":1776865116965,"version":"3.51.2"},"reference-count":27,"publisher":"MDPI AG","issue":"8","license":[{"start":{"date-parts":[[2009,7,27]],"date-time":"2009-07-27T00:00:00Z","timestamp":1248652800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames\/s (fps). A prototype chip with 64 \u00d7 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mm Standard CMOS process. The area size of chip is 1.5 mm \u00d7 3.5 mm. Each pixel size is 9.5 \u03bcm \u00d7 9.5 \u03bcm and each processing element size is 23 \u03bcm \u00d7 29 \u03bcm. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.<\/jats:p>","DOI":"10.3390\/s90805933","type":"journal-article","created":{"date-parts":[[2009,7,27]],"date-time":"2009-07-27T12:19:08Z","timestamp":1248697148000},"page":"5933-5951","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":19,"title":["A 1,000 Frames\/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors"],"prefix":"10.3390","volume":"9","author":[{"given":"Qingyu","family":"Lin","sequence":"first","affiliation":[{"name":"State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei","family":"Miao","sequence":"additional","affiliation":[{"name":"State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wancheng","family":"Zhang","sequence":"additional","affiliation":[{"name":"State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qiuyu","family":"Fu","sequence":"additional","affiliation":[{"name":"State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nanjian","family":"Wu","sequence":"additional","affiliation":[{"name":"State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2009,7,27]]},"reference":[{"key":"ref_1","first-page":"580","article-title":"Computational sensors\u2014vision VLSI","volume":"E82-D","author":"Aizawa","year":"1999","journal-title":"IEICE Trans. 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