{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T15:50:53Z","timestamp":1774367453730,"version":"3.50.1"},"reference-count":18,"publisher":"MDPI AG","issue":"2","license":[{"start":{"date-parts":[[2019,1,30]],"date-time":"2019-01-30T00:00:00Z","timestamp":1548806400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61504169"],"award-info":[{"award-number":["61504169"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Symmetry"],"abstract":"<jats:p>In a triple-well NMOSFET, a deep n+ well (DNW) is buried in the substrate to isolate the substrate noise. The presence of this deep n+ well leads to changes in single-event transient effects compared to bulk NMOSFET. In space, a single cosmic particle can deposit enough charge in the sensitive volume of a semiconductor device to cause a potential change in the transient state, that is, a single-event transient (SET). In this study, a quantitative characterization of the effect of a DNW on a SET in a 65 nm triple-well NMOSFET was performed using heavy ion experiments. Compared with a bulk NMOSFET, the experimental data show that the percentages of average increase of a SET pulse width are 22% (at linear energy transfer (LET) = 37.4 MeV\u00b7cm2\/mg) and 23% (at LET = 22.2 MeV\u00b7cm2\/mg) in a triple-well NMOSFET. This study indicates that a triple-well NMOSFET is more sensitive to a SET, which means that it may not be appropriate for radiation hardened integrated circuit design compared with a bulk NMOSFET.<\/jats:p>","DOI":"10.3390\/sym11020154","type":"journal-article","created":{"date-parts":[[2019,1,30]],"date-time":"2019-01-30T10:58:27Z","timestamp":1548845907000},"page":"154","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["The Effect of Deep N+ Well on Single-Event Transient in 65 nm Triple-Well NMOSFET"],"prefix":"10.3390","volume":"11","author":[{"given":"Jizuo","family":"Zhang","sequence":"first","affiliation":[{"name":"College of Computer, National University of Defense Technology, Changsha 410073, Hunan, China"},{"name":"Hunan University of Humanities Science and Technology, Loudi 417000, Hunan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jianjun","family":"Chen","sequence":"additional","affiliation":[{"name":"College of Computer, National University of Defense Technology, Changsha 410073, Hunan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pengcheng","family":"Huang","sequence":"additional","affiliation":[{"name":"College of Computer, National University of Defense Technology, Changsha 410073, Hunan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shouping","family":"Li","sequence":"additional","affiliation":[{"name":"College of Computer, National University of Defense Technology, Changsha 410073, Hunan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liang","family":"Fang","sequence":"additional","affiliation":[{"name":"College of Computer, National University of Defense Technology, Changsha 410073, Hunan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2019,1,30]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"1767","DOI":"10.1109\/TNS.2013.2255624","article-title":"Single event transients in digital CMOS A review","volume":"60","author":"Cavrois","year":"2013","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"271","DOI":"10.1007\/s11431-012-5070-8","article-title":"Novel N-hit single event transient mitigation technique via open guard transistor in 65 nm bulk CMOS process","volume":"56","author":"Huang","year":"2013","journal-title":"Sci. China Tech. Sci."},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"867","DOI":"10.1007\/s11431-012-4753-5","article-title":"Single event transient pulse attenuation effect in three-transistor inverter chain","volume":"55","author":"Chen","year":"2012","journal-title":"Sci. China Tech. Sci."},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"3253","DOI":"10.1109\/TNS.2006.884788","article-title":"Charge collection and charge sharing in a 130 nm C-MOS technology","volume":"53","author":"Amusan","year":"2006","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_5","first-page":"3386","article-title":"Independent measurement of SET pulse widths from N-hits and P-hits in 65-nm CMOS","volume":"57","author":"Jagannathan","year":"2010","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"179","DOI":"10.1109\/TDMR.2010.2102354","article-title":"Single-event transient measurements in nMOS and pMOS transistors in a 65-nm bulk CM-OS technology at elevated temperatures","volume":"1","author":"Gadlage","year":"2011","journal-title":"IEEE Trans. Device Mater. Rel."},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"2060","DOI":"10.1109\/TNS.2007.907754","article-title":"Design techniques to reduce SET pulse widths in deep-submicron combinational logic","volume":"54","author":"Amusan","year":"2007","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"2948","DOI":"10.1109\/TNS.2008.2005831","article-title":"single Event Mechanisms in 90 nm Triple-Well CMOS Devices","volume":"55","author":"Roy","year":"2008","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"99","DOI":"10.1109\/TDMR.2013.2290032","article-title":"Simulation study of the selectively implanted deep-N-well for PMOS SET mitigation","volume":"14","author":"He","year":"2014","journal-title":"IEEE Trans. Device Mater. Rel."},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"2859","DOI":"10.1109\/TNS.2012.2212457","article-title":"Novel layout technique for N-hit single-event transient mitigation via source-extension","volume":"59","author":"Chen","year":"2012","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"1227","DOI":"10.1016\/j.microrel.2011.12.002","article-title":"Radiation hardened by design techniques to reduce single event transient pulse width based on the physical mechanism","volume":"52","author":"Chen","year":"2012","journal-title":"Microelectron. Reliab."},{"key":"ref_12","doi-asserted-by":"crossref","first-page":"177","DOI":"10.1109\/TDMR.2012.2227261","article-title":"Novel layout technique for single-event transient mitigation using dummy transistor","volume":"13","author":"Chen","year":"2012","journal-title":"IEEE Trans. Device Mater. Rel."},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"501","DOI":"10.1109\/TDMR.2012.2191971","article-title":"Simulation study of the layout technique for P-hit single-event transient mitigation via the source-isolation","volume":"12","author":"Chen","year":"2012","journal-title":"IEEE Trans. Device Mater. Rel."},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"2302","DOI":"10.1109\/TNS.2015.2469740","article-title":"Characterization of single-event transient pulse quenching among dummy gate isolated logic nodes in 65nm twin-well and triple-well CMOS technologies","volume":"62","author":"Chen","year":"2015","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"2259","DOI":"10.1109\/JSSC.2004.836338","article-title":"An ultra-wideband CMOS low noise amplifier for 3.1\u201310.6-GHz wireless receivers","volume":"39","author":"Bevilacqua","year":"2004","journal-title":"IEEE J. Solid-St Circ."},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"1726","DOI":"10.1007\/s11431-015-5906-0","article-title":"Characterizations of the effect of vertical well isolation on single-event multiple cell upsets in SRAM in a 65nm triple-well CMOS technology","volume":"58","author":"Chen","year":"2015","journal-title":"Sci. China Tech. Sci."},{"key":"ref_17","doi-asserted-by":"crossref","first-page":"542","DOI":"10.1109\/TDMR.2006.885589","article-title":"On-chip Characterization of single-Event Transient Pulsewiths","volume":"6","author":"Narasimham","year":"2006","journal-title":"IEEE Trans. Device Mater. Rel."},{"key":"ref_18","doi-asserted-by":"crossref","first-page":"49","DOI":"10.1007\/s41365-018-0391-3","article-title":"Analysis of Single-Event Transient Sensitivity in Fully-Depleted Silicon-on-Insulator MOSFETs","volume":"29","author":"Xu","year":"2018","journal-title":"Nucl. Sci. Tech."}],"container-title":["Symmetry"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2073-8994\/11\/2\/154\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T12:29:43Z","timestamp":1760185783000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2073-8994\/11\/2\/154"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,1,30]]},"references-count":18,"journal-issue":{"issue":"2","published-online":{"date-parts":[[2019,2]]}},"alternative-id":["sym11020154"],"URL":"https:\/\/doi.org\/10.3390\/sym11020154","relation":{},"ISSN":["2073-8994"],"issn-type":[{"value":"2073-8994","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,1,30]]}}}