{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,14]],"date-time":"2025-10-14T00:41:51Z","timestamp":1760402511407,"version":"build-2065373602"},"reference-count":7,"publisher":"MDPI AG","issue":"1","license":[{"start":{"date-parts":[[2020,1,14]],"date-time":"2020-01-14T00:00:00Z","timestamp":1578960000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"National Natural Science Foundation of China Program","award":["61772540"],"award-info":[{"award-number":["61772540"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Symmetry"],"abstract":"<jats:p>This paper presents a foreground digital calibration algorithm based on a dynamic comparator that aims to reduce comparator offset and capacitor mismatch, as well as improve the performance of the successive approximation analog-to-digital converter (SARADC). The dynamic comparator is designed with two preamplifiers and one latch to facilitate high speed, high precision, and low noise. The foreground digital calibration algorithm provides high speed with minimal area consumption. This design is implemented on a 12-bit 30 MS\/s SARADC with a standard 0.13 \u03bcm Complementary Metal Oxide Semiconductor (CMOS) process. The simulation Nyquist 68.56 dB signal-to-noise-and-distortion ratio (SNDR) and 84.45 dBc spurious free dynamic range (SFDR) at 30 MS\/s, differential nonlinearity (DNL) and integral nonlinearity (INL) are within 0.64 Least Significant Bits (LSB) and 1.3 LSB, respectively. The ADC achieves an effective number of bits (ENOB) of 11.08 and a figure-of-merit (FoM) of 39.45 fJ\/conv.-step.<\/jats:p>","DOI":"10.3390\/sym12010165","type":"journal-article","created":{"date-parts":[[2020,1,15]],"date-time":"2020-01-15T03:20:22Z","timestamp":1579058422000},"page":"165","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A 12-bit 30 MS\/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm"],"prefix":"10.3390","volume":"12","author":[{"given":"Shouping","family":"Li","sequence":"first","affiliation":[{"name":"Department of Microelectronics, College of Computer Science, National University of Defense Technology, Changsha 410073, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yang","family":"Guo","sequence":"additional","affiliation":[{"name":"Department of Microelectronics, College of Computer Science, National University of Defense Technology, Changsha 410073, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0574-6608","authenticated-orcid":false,"given":"Jianjun","family":"Chen","sequence":"additional","affiliation":[{"name":"Department of Microelectronics, College of Computer Science, National University of Defense Technology, Changsha 410073, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bin","family":"Liang","sequence":"additional","affiliation":[{"name":"Department of Microelectronics, College of Computer Science, National University of Defense Technology, Changsha 410073, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2020,1,14]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"1149","DOI":"10.1109\/JSSC.2017.2784761","article-title":"A 16-bit 16 MS\/s SAR ADC with on-chip calibration in 55 nm CMOS","volume":"53","author":"Shen","year":"2018","journal-title":"IEEE J. Solid-State Circuits."},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"42930","DOI":"10.1109\/ACCESS.2018.2852729","article-title":"Exploiting Smallest Error to Calibrate Non-Linearity in SAR Adcs","volume":"6","author":"Fan","year":"2018","journal-title":"IEEE Access"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"789","DOI":"10.1109\/JSSC.2017.2768404","article-title":"A 6-bit 0.81-mW 700-MS\/s SAR ADC with sparkle-code correction, resolution enhancement, and background window width calibration","volume":"53","author":"Yoon","year":"2018","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"482","DOI":"10.1049\/el.2011.4001","article-title":"Low-energy and area-efficient tri-level switching scheme for SAR ADC","volume":"48","author":"Yuan","year":"2012","journal-title":"Electron. Lett."},{"doi-asserted-by":"crossref","unstructured":"Tang, X., Chen, L., and Song, J. (2017, January 1\u20134). A 1.5fJ\/conv-step 10b 100kS\/s SAR ADC with gain-boosted dynamic comparator. Proceedings of the IEEE Asian Solid-State Circuits Conference: ASSCC 2017, Seoul, Korea.","key":"ref_5","DOI":"10.1109\/ASSCC.2017.8240258"},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"1881","DOI":"10.1109\/JSSC.2011.2151450","article-title":"A 550-\u03bcW 10-b 40-MS\/s SAR ADC with Multistep Addition-Only Digital Error Correction","volume":"46","author":"Cho","year":"2011","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_7","first-page":"26","article-title":"A speed-enhancing dual-trial instantaneous switching architecture for SAR ADCs","volume":"62","author":"He","year":"2015","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"}],"container-title":["Symmetry"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2073-8994\/12\/1\/165\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,13]],"date-time":"2025-10-13T13:42:58Z","timestamp":1760362978000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2073-8994\/12\/1\/165"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,1,14]]},"references-count":7,"journal-issue":{"issue":"1","published-online":{"date-parts":[[2020,1]]}},"alternative-id":["sym12010165"],"URL":"https:\/\/doi.org\/10.3390\/sym12010165","relation":{},"ISSN":["2073-8994"],"issn-type":[{"type":"electronic","value":"2073-8994"}],"subject":[],"published":{"date-parts":[[2020,1,14]]}}}