{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T03:22:34Z","timestamp":1760239354803,"version":"build-2065373602"},"reference-count":12,"publisher":"MDPI AG","issue":"11","license":[{"start":{"date-parts":[[2020,10,23]],"date-time":"2020-10-23T00:00:00Z","timestamp":1603411200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"National Natural Science Foundation of China Program","award":["61772540","61974163"],"award-info":[{"award-number":["61772540","61974163"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Symmetry"],"abstract":"<jats:p>This paper proposed a digital background calibration algorithm with positive and negative symmetry error tolerance to remedy the capacitor mismatch for successive approximation register analog-to-digital converters (SAR ADCs). Compensate for the errors caused by capacitor mismatches and improve the ADC performance. Combination with a tri-level switching scheme based on the common-mode voltage Vcm to achieve capacitor reduction and high switching energy efficiency. The proposed calibration algorithm significantly improves capacitor mismatch without resorting to extensive computation or dedicated circuits. The active area is 0.046 mm2 in 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The post-simulation results show the effective number of bits (ENOB) improves from 8.23 bits to 11.36 bits, signal-to-noise-and distortion ratio (SNDR) improves from 51.33 dB to 70.15 dB, respectively, before and after calibration. This improves the spurious-free dynamic range (SFDR) by 24.13 dB, from 61.50 dB up to 85.63 dB. The whole ADC\u2019s power consumption is only 0.3564 mW at sampling rate fs =2 MS\/s and Nyquist input frequency, with a figure-of-merit (FOM) 67.8 fJ\/conv.-step.<\/jats:p>","DOI":"10.3390\/sym12111757","type":"journal-article","created":{"date-parts":[[2020,10,23]],"date-time":"2020-10-23T08:59:28Z","timestamp":1603443568000},"page":"1757","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Low Power SAR ADC Design with Digital Background Calibration Algorithm"],"prefix":"10.3390","volume":"12","author":[{"given":"Shouping","family":"Li","sequence":"first","affiliation":[{"name":"Department of Microelectronics, College of Computer Science, National University of Defense Technology, Changsha 410073, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jianjun","family":"Chen","sequence":"additional","affiliation":[{"name":"Department of Microelectronics, College of Computer Science, National University of Defense Technology, Changsha 410073, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bin","family":"Liang","sequence":"additional","affiliation":[{"name":"Department of Microelectronics, College of Computer Science, National University of Defense Technology, Changsha 410073, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yang","family":"Guo","sequence":"additional","affiliation":[{"name":"Department of Microelectronics, College of Computer Science, National University of Defense Technology, Changsha 410073, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2020,10,23]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Liu, W., Huang, P., and Chiu, Y. (2010, January 7\u201311). A 12b 22.5\/45MS\/s 3.0 mW 0.059 mm2 CMOS SAR ADC Achieving over 90dB SFDR. Proceedings of the 2010 IEEE International Solid-State Circuits Conference\u2014(ISSCC), San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2010.5433830"},{"key":"ref_2","first-page":"1785","article-title":"A General Purpose 1.8-V 12-b 4-MS\/s Fully Differential SAR ADC With 7.2-Vpp Input Range in 28-nm FDSOI","volume":"66","author":"Berens","year":"2019","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"881","DOI":"10.1109\/TCSI.2017.2771364","article-title":"A 12-b 40-MS\/s Calibration-Free SAR ADC","volume":"65","author":"Hsu","year":"2018","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"2951","DOI":"10.1109\/JSSC.2016.2591553","article-title":"A 0.076 mm2 12 b 26.5 mW 600 MS\/s 4-Way Interleaved Subranging SAR-\u0394\u03a3 ADC With On-Chip Buffer in 28 nm CMOS","volume":"51","author":"Venca","year":"2016","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"1203","DOI":"10.1109\/TVLSI.2015.2442258","article-title":"Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS\/s SAR ADC","volume":"24","author":"Zhu","year":"2016","journal-title":"IEEE Trans. Large Scale Integr. (VLSI) Syst."},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"984","DOI":"10.1049\/el.2019.0872","article-title":"Dither-based background calibration of capacitor mismatch and gain error in pipelined noise shaping successive approximation register ADCs","volume":"55","author":"Wang","year":"2019","journal-title":"Electron. Lett."},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"95","DOI":"10.1109\/LSSC.2019.2931606","article-title":"A Capacitor Dielectric Relaxation Effect Cancellation Circuit in a 12-Bit, 1-MSps, 5.0-V SAR ADC on a 28-nm Embedded Flash Memory Microcontroller","volume":"2","author":"Matsui","year":"2019","journal-title":"IEEE Solid-State Circuits Lett."},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"2941","DOI":"10.1109\/JSSC.2016.2591822","article-title":"A 12 bit 100 MS\/s SAR-Assisted Digital-Slope ADC","volume":"51","author":"Liu","year":"2016","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"1989","DOI":"10.1109\/TVLSI.2018.2849008","article-title":"A 12-bit 40-MS\/s SAR ADC with a Fast-Binary-Window DAC Switching Scheme","volume":"26","author":"Chung","year":"2018","journal-title":"IEEE Trans. Large Scale Integr. (VLSI) Syst."},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"1684","DOI":"10.1109\/TCSI.2017.2679748","article-title":"A 12b 180MS\/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC","volume":"64","author":"Zhong","year":"2017","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"358","DOI":"10.1109\/TCSI.2019.2922726","article-title":"A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme","volume":"67","author":"Chung","year":"2020","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_12","first-page":"1589","article-title":"A Mismatch-Immune 12-Bit SAR ADC with Completely Reconfigurable Capacitor DAC","volume":"65","author":"Collins","year":"2018","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"}],"container-title":["Symmetry"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2073-8994\/12\/11\/1757\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T10:26:37Z","timestamp":1760178397000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2073-8994\/12\/11\/1757"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10,23]]},"references-count":12,"journal-issue":{"issue":"11","published-online":{"date-parts":[[2020,11]]}},"alternative-id":["sym12111757"],"URL":"https:\/\/doi.org\/10.3390\/sym12111757","relation":{},"ISSN":["2073-8994"],"issn-type":[{"type":"electronic","value":"2073-8994"}],"subject":[],"published":{"date-parts":[[2020,10,23]]}}}