{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,24]],"date-time":"2026-01-24T17:57:59Z","timestamp":1769277479863,"version":"3.49.0"},"reference-count":40,"publisher":"MDPI AG","issue":"10","license":[{"start":{"date-parts":[[2021,10,2]],"date-time":"2021-10-02T00:00:00Z","timestamp":1633132800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100002349","name":"Academy of Scientific Research and Technology","doi-asserted-by":"publisher","award":["6614"],"award-info":[{"award-number":["6614"]}],"id":[{"id":"10.13039\/501100002349","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Symmetry"],"abstract":"<jats:p>Reversible arithmetic and logic unit (ALU) is a necessary part of quantum computing. In this work, we present improved designs of reversible half and full addition and subtraction circuits. The proposed designs are based on a universal one type gate (G gate library). The G gate library can generate all possible permutations of the symmetric group. The presented designs are multi-function circuits that are capable of performing additional logical operations. We achieve a reduction in the quantum cost, gate count, number of constant inputs, and delay with zero garbage, compared to relevant results obtained by others. The experimental results using IBM Quantum Experience (IBM Q) illustrate the success probability of the proposed designs.<\/jats:p>","DOI":"10.3390\/sym13101842","type":"journal-article","created":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T01:59:47Z","timestamp":1633917587000},"page":"1842","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Efficient Designs of Quantum Adder\/Subtractor Using Universal Reversible Gate on IBM Q"],"prefix":"10.3390","volume":"13","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4841-1955","authenticated-orcid":false,"given":"Mohamed","family":"Osman","sequence":"first","affiliation":[{"name":"Department of Mathematics, Faculty of Science, Damanhour University, Damanhour 22511, Egypt"},{"name":"Academy of Scientific Research and Technology (ASRT), Cairo 11516, Egypt"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8193-1602","authenticated-orcid":false,"given":"Khaled","family":"El-Wazan","sequence":"additional","affiliation":[{"name":"Academy of Scientific Research and Technology (ASRT), Cairo 11516, Egypt"},{"name":"Department of Mathematics and Computer Science, Faculty of Science, Alexandria University, Alexandria 21568, Egypt"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2021,10,2]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"525","DOI":"10.1147\/rd.176.0525","article-title":"Logical reversibility of computation","volume":"17","author":"Bennett","year":"1973","journal-title":"IBM J. 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