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Application mapping is the first and most important step in the NoC synthesis flow, which determines most of the NoC design performance. NoC mapping has been confirmed as an NP-hard (Non-Polynomial hard) problem, which could not be solved in polynomial time. Various heuristic mapping algorithms have been applied to the mapping problem. However, the heuristic algorithm easily falls into a local optimal solution which causes performance loss. Additionally, regular topologies of NoC, such as the ring, torus, etc., may generate symmetric solutions in the NoC mapping process, which increase the performance loss. Machine learning involves data-driven methods to analyze trends, find relationships, and develop models to predict things based on datasets. In this paper, an NoC machine learning mapping algorithm is proposed to solve a mapping problem. A Low-complexity and no symmetry NoC mapping dataset is defined, and a data augmentation approach is proposed to build dataset. With the dataset defined, a multi-label machine learning is established. The simulation results have confirmed that the machine learning mapping algorithm is proposed have at least 99.6% model accuracy and an average of 96.3% mapping accuracy.<\/jats:p>","DOI":"10.3390\/sym15030593","type":"journal-article","created":{"date-parts":[[2023,2,27]],"date-time":"2023-02-27T04:05:40Z","timestamp":1677470740000},"page":"593","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["A Machine Learning Mapping Algorithm for NoC Optimization"],"prefix":"10.3390","volume":"15","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9628-0945","authenticated-orcid":false,"given":"Xiaodong","family":"Weng","sequence":"first","affiliation":[{"name":"School of Microelectronics, Xidian University, Xi\u2019an 710126, China"}]},{"given":"Yi","family":"Liu","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Xidian University, Xi\u2019an 710126, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3827-8820","authenticated-orcid":false,"given":"Changqing","family":"Xu","sequence":"additional","affiliation":[{"name":"Guangzhou Institute of Technology, Xidian University, Guangzhou 510555, China"}]},{"given":"Xiaoling","family":"Lin","sequence":"additional","affiliation":[{"name":"Technology on Reliability Physics and Application Technology of Electronic Component Laboratory, China Electronic Product Reliability and Environmental Testing Research Institute, Guangzhou 510610, China"}]},{"given":"Linjun","family":"Zhan","sequence":"additional","affiliation":[{"name":"Guangzhou Institute of Technology, Xidian University, Guangzhou 510555, China"}]},{"given":"Shunyao","family":"Wang","sequence":"additional","affiliation":[{"name":"Guangzhou Institute of Technology, Xidian University, Guangzhou 510555, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5065-4374","authenticated-orcid":false,"given":"Dongdong","family":"Chen","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Xidian University, Xi\u2019an 710126, China"}]},{"given":"Yintang","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Xidian University, Xi\u2019an 710126, China"}]}],"member":"1968","published-online":{"date-parts":[[2023,2,25]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1016\/j.sysarc.2014.11.001","article-title":"Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores","volume":"61","author":"Soumya","year":"2014","journal-title":"J. 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