{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,20]],"date-time":"2026-06-20T16:22:39Z","timestamp":1781972559941,"version":"3.54.5"},"reference-count":32,"publisher":"MDPI AG","issue":"6","license":[{"start":{"date-parts":[[2023,6,16]],"date-time":"2023-06-16T00:00:00Z","timestamp":1686873600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"National Key Research and Development Program of China","award":["2019YFB1706800"],"award-info":[{"award-number":["2019YFB1706800"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Symmetry"],"abstract":"<jats:p>Layout stitching is a repetitive and tedious task of the radio frequency integrated circuit (RFIC) design process. While academic research on layout splicing algorithms mainly focuses on analog and digital circuits, there is still a lack of well-developed algorithms for RFICs. An RFIC system usually has a symmetrical layout, such as transmitter and receiver components, low-noise amplifier (LNA), an SPDT switch, etc. This paper aims to address this gap by proposing an automated procedure for the layout of RFICs by relying on the basic device\/PCell structure based on the interconnection among circuit topologies. This approach makes the in-series generation of layouts and automatic splicing based on circuit logic possible, resulting in superior stitching performance compared with related modules in Advanced Design System. To demonstrate the physical application possibilities, we implemented our algorithm on an LNA and a switch circuit.<\/jats:p>","DOI":"10.3390\/sym15061272","type":"journal-article","created":{"date-parts":[[2023,6,16]],"date-time":"2023-06-16T08:56:01Z","timestamp":1686905761000},"page":"1272","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["From Netlist to Manufacturable Layout: An Auto-Layout Algorithm Optimized for Radio Frequency Integrated Circuits"],"prefix":"10.3390","volume":"15","author":[{"given":"Yiding","family":"Wei","sequence":"first","affiliation":[{"name":"Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jun","family":"Liu","sequence":"additional","affiliation":[{"name":"Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dengbao","family":"Sun","sequence":"additional","affiliation":[{"name":"Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6927-9183","authenticated-orcid":false,"given":"Guodong","family":"Su","sequence":"additional","affiliation":[{"name":"Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Junchao","family":"Wang","sequence":"additional","affiliation":[{"name":"Zhejiang Provincial Key Laboratory of Large Scale Integrated Circuit Design, School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"1968","published-online":{"date-parts":[[2023,6,16]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Novichkova, Y.A., Fail, T.N., Goryainov, A.E., Kalentyev, A.A., Bilevich, D.V., and Dobush, I.M. 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