{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,10]],"date-time":"2025-10-10T01:46:08Z","timestamp":1760060768751,"version":"build-2065373602"},"reference-count":47,"publisher":"MDPI AG","issue":"10","license":[{"start":{"date-parts":[[2025,10,9]],"date-time":"2025-10-09T00:00:00Z","timestamp":1759968000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Symmetry"],"abstract":"<jats:p>The integration of AI-driven optimization into Electronic Design Automation (EDA) enables smarter and more adaptive circuit design, where symmetry and asymmetry play key roles in balancing performance, robustness, and manufacturability. This work presents a model-driven optimization methodology for sizing low-phase-noise LC voltage-controlled oscillators (VCOs) at 5 GHz, targeting Wi-Fi, 5G, and automotive radar applications. The approach uses the EKV transistor model for analytical CMOS device characterization and applies a diverse set of metaheuristic algorithms for both single-objective (phase noise minimization) and multi-objective (joint phase noise and power) optimization. A central focus is on how symmetry\u2014embedded in the complementary cross-coupled LC-VCO topology\u2014and asymmetry\u2014introduced by parasitics, mismatch, and layout constraints\u2014affect optimization outcomes. The methodology implicitly captures these effects during simulation-based optimization, enabling design-space exploration that is both symmetry-aware and robust to unavoidable asymmetries. Implemented in CMOS 180 nm technology, the approach delivers designs with improved phase noise and power efficiency while ensuring manufacturability. Yield analysis confirms that integrating symmetry considerations into metaheuristic-based optimization enhances performance predictability and resilience to process variations, offering a scalable, AI-aligned solution for high-performance analog circuit design within EDA workflows.<\/jats:p>","DOI":"10.3390\/sym17101693","type":"journal-article","created":{"date-parts":[[2025,10,9]],"date-time":"2025-10-09T16:54:31Z","timestamp":1760028871000},"page":"1693","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Symmetry-Aware EKV-Based Metaheuristic Optimization of CMOS LC-VCOs for Low-Phase-Noise Applications"],"prefix":"10.3390","volume":"17","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4875-8577","authenticated-orcid":false,"given":"Abdelaziz","family":"Lberni","sequence":"first","affiliation":[{"name":"SI Laboratory, Polydisciplinary Faculty of Taza, University of Sidi Mohamed Ben Abdellah, Taza P.O. Box 1223, Morocco"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9106-8972","authenticated-orcid":false,"given":"Malika Alami","family":"Marktani","sequence":"additional","affiliation":[{"name":"LaRSI, National School of Applied Sciences, University of Sidi Mohamed Ben Abdellah, Fez P.O. Box 72, Morocco"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5310-1388","authenticated-orcid":false,"given":"Abdelaziz","family":"Ahaitouf","sequence":"additional","affiliation":[{"name":"SI Laboratory, Polydisciplinary Faculty of Taza, University of Sidi Mohamed Ben Abdellah, Taza P.O. Box 1223, Morocco"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1133-1887","authenticated-orcid":false,"given":"Ali","family":"Ahaitouf","sequence":"additional","affiliation":[{"name":"LaRSI, \u00c9cole Normale Sup\u00e9rieur, B.P. 5206, Bensouda, Fez P.O. Box 2202, Morocco"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2025,10,9]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"3773","DOI":"10.1109\/TMTT.2018.2840982","article-title":"Cu\/co multilayer-based high signal integrity and low rf loss conductors for 5 g\/millimeter wave applications","volume":"66","author":"Hwangbo","year":"2018","journal-title":"IEEE Trans. Microw. Theory Tech."},{"key":"ref_2","unstructured":"Kazuma, O., Yuka, K., Hiroyuki, I., Kenichi, O., Hideki, H., Takuya, A., Tatsuya, I., Ryozo, Y., and Kazuya, M. (2008, January 15\u201317). A low phase noise lc-vco with a high-q inductor fabricated by wafer level package technology. Proceedings of the 2008 IEEE Radio Frequency Integrated Circuits Symposium, Atlanta, GA, USA."},{"key":"ref_3","unstructured":"Baker, R.J. (2019). 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