{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T04:10:27Z","timestamp":1760242227109,"version":"build-2065373602"},"reference-count":9,"publisher":"MDPI AG","issue":"1","license":[{"start":{"date-parts":[[2017,1,22]],"date-time":"2017-01-22T00:00:00Z","timestamp":1485043200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Symmetry"],"abstract":"<jats:p>This paper presents a fully integrated on-chip switched-capacitor (SC) DC\u2013DC converter that supports a programmable regulated power supply ranging from 2.6 to 3.2 V out of a 5 V input supply. The proposed 4-to-3 step-down topology utilizes two conventional 2-to-1 step-down topologies; each of them (2-to-1_up and 2-to-1_dw) has a different flying capacitance to maximize the load current driving capability while minimizing the bottom-plate capacitance loss. The control circuits use a low power supply provided by a small internal low-drop output (LDO) connected to the internal load voltage (VL_dw) from the 2-to-1_dw, and low swing level-shifted gate-driving signals are generated using the internal load voltage (VL_dw). Therefore, the proposed implementation reduces control circuit and switching power consumptions. The programmable power supply voltage is regulated by means of a pulse frequency modulation (PFM) technique with the compensated two-stage operational transconductance amplifier (OTA) and the current-starved voltage controlled oscillator (VCO) to maintain high efficiency over a wide range of load currents. The proposed on-chip SC DC\u2013DC converter is designed and simulated using high-voltage 0.35 \u03bcm bipolar, complementary metal-oxide-semiconductor (CMOS) and DMOS (BCDMOS) technology. It achieves a peak efficiency of 74% when delivering an 8 mA load current at a 3.2 V supply voltage level, and it provides a maximum output power of 48 mW (IL = 15 mA at VL_up = 3.2 V) at 70.5% efficiency. The proposed on-chip SC voltage regulator shows better efficiency than the ideal linear regulator over a wide range of output power, from 2.6 mW to 48 mW. The 18-phase interleaving technique enables the worst-case output voltage ripple to be less than 5.77% of the load voltage.<\/jats:p>","DOI":"10.3390\/sym9010018","type":"journal-article","created":{"date-parts":[[2017,1,23]],"date-time":"2017-01-23T10:40:33Z","timestamp":1485168033000},"page":"18","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["Fully Integrated on-Chip Switched DC\u2013DC Converter for Battery-Powered Mixed-Signal SoCs"],"prefix":"10.3390","volume":"9","author":[{"given":"Heungjun","family":"Jeon","sequence":"first","affiliation":[{"name":"Samsung Electronics Co., Ltd., Gyeonggi-do 16677, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kyung","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Daegu University, Gyeongsan 38453, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yong-Bin","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Northeastern University, 360 Huntington Ave., Boston, MA 02115, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2017,1,22]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"2557","DOI":"10.1109\/JSSC.2010.2076550","article-title":"A fully-integrated switched-capacitor step-down DC-DC converter with digital capacitance modulation in 45 nm CMOS","volume":"45","author":"Ramadass","year":"2010","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"2120","DOI":"10.1109\/JSSC.2011.2159054","article-title":"Design techniques for fully integrated switched-capacitor DC-DC converters","volume":"46","author":"Le","year":"2011","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"1715","DOI":"10.1109\/JSSC.2011.2144350","article-title":"Monolithic capacitive DC-DC converter with single boundary-multiphase control and voltage domain stacking in 90 nm CMOS","volume":"46","author":"Steyaert","year":"2011","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_4","unstructured":"Jain, R., and Sanders, S. (September, January 30). A 200 mA switched capacitor voltage regulator on 32 nm CMOS and regulation schemes to enable DVFS. Proceedings of the 14th European Conference on Power Electronics and Applications (EPE 2011), Birmingham, UK."},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"280","DOI":"10.1109\/TCSI.2009.2019394","article-title":"Design and analysis of monolithic step-down SC power converter with subthreshold DPWM control for self-powered wireless sensors","volume":"57","author":"Su","year":"2010","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_6","doi-asserted-by":"crossref","unstructured":"Baker, R.J. (2010). CMOS Circuits Design, Layout, and Simulation, Wiley-IEEE Press. [3rd ed.].","DOI":"10.1002\/9780470891179"},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"670","DOI":"10.1109\/4.760378","article-title":"A CMOS bandgap reference circuit with sub-1-V operation","volume":"34","author":"Banba","year":"1999","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_8","doi-asserted-by":"crossref","unstructured":"Viraj, A., and Amaratunga, G. (2007, January 17\u201321). A monolithic CMOS 5V\/1V switched capacitor DC\u2013DC step-down converter. Proceedings of the Power Electronics Specialists Conference (PESC 2007), Orlando, FL, USA.","DOI":"10.1109\/PESC.2007.4342408"},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"Wei, C.-L., and Yang, H.-H. (June, January 30). Analysis and design of a step-down switched-capacitor-based converter for low-power application. Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France.","DOI":"10.1109\/ISCAS.2010.5537942"}],"container-title":["Symmetry"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2073-8994\/9\/1\/18\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T18:26:46Z","timestamp":1760207206000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2073-8994\/9\/1\/18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,1,22]]},"references-count":9,"journal-issue":{"issue":"1","published-online":{"date-parts":[[2017,1]]}},"alternative-id":["sym9010018"],"URL":"https:\/\/doi.org\/10.3390\/sym9010018","relation":{},"ISSN":["2073-8994"],"issn-type":[{"type":"electronic","value":"2073-8994"}],"subject":[],"published":{"date-parts":[[2017,1,22]]}}}