{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,22]],"date-time":"2026-09-22T10:03:50Z","timestamp":1790071430750,"version":"4.0.1"},"reference-count":37,"publisher":"MDPI AG","issue":"9","license":[{"start":{"date-parts":[[2026,9,18]],"date-time":"2026-09-18T00:00:00Z","timestamp":1789689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J. Imaging"],"abstract":"<jats:p>This paper presents a stage-complete programmable-logic architecture for pairwise monocular structure from motion using calibrated, pre-undistorted 1920 \u00d7 1080 video. It integrates streaming feature extraction, Block-RAM-backed Top-K selection, spatial-bucket matching, two-pass essential-matrix estimation and pruning, fixed-point pose recovery, and triangulation with point-coordinate output. Bounded feature storage, local correspondence search, and mixed floating- and fixed-point arithmetic support the complete pairwise chain without processor-side geometry computation. The complete VCU118\/XCVU9P design was synthesized, placed, routed, and compiled to a bitstream in Vivado 2026.1, meeting setup and hold timing with +0.031 ns and +0.010 ns slack, respectively. It uses 12.09% of the device\u2019s logic lookup tables and 32.94% of its Block RAM tiles. Controlled numerical tests characterize the operating domain of the geometry stages. The cycle-based model estimates a 13.13 ms geometry-back-end subtotal at 1000 matches; 60 fps is the architectural input target. To the authors\u2019 knowledge, within the directly comparable literature surveyed, this is the first reported stage-complete mapping of the listed pairwise chain entirely to programmable logic.<\/jats:p>","DOI":"10.3390\/jimaging12090451","type":"journal-article","created":{"date-parts":[[2026,9,22]],"date-time":"2026-09-22T08:17:54Z","timestamp":1790065074000},"page":"451","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Stage-Complete Mapping of Pairwise Monocular Structure-from-Motion to Field-Programmable Gate Arrays"],"prefix":"10.3390","volume":"12","author":[{"ORCID":"https:\/\/orcid.org\/0009-0006-1568-8137","authenticated-orcid":false,"given":"Panteleimon","family":"Stamatakis","sequence":"first","affiliation":[{"name":"Department of Computer, Informatics & Telecommunications Engineering, International Hellenic University, 62121 Serres, Greece"}],"role":[{"vocabulary":"crossref","role":"author"},{"role":"conceptualization","vocabulary":"credit"},{"role":"investigation","vocabulary":"credit"},{"role":"methodology","vocabulary":"credit"},{"role":"software","vocabulary":"credit"},{"role":"validation","vocabulary":"credit"},{"role":"writing-original-draft","vocabulary":"credit"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3709-6395","authenticated-orcid":false,"given":"John","family":"Vourvoulakis","sequence":"additional","affiliation":[{"name":"Department of Computer, Informatics & Telecommunications Engineering, International Hellenic University, 62121 Serres, Greece"}],"role":[{"vocabulary":"crossref","role":"author"},{"role":"writing-review-editing","vocabulary":"credit"}]}],"member":"1968","published-online":{"date-parts":[[2026,9,18]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Hartley, R., and Zisserman, A. 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