{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,18]],"date-time":"2026-08-18T04:56:12Z","timestamp":1787028972739,"version":"build-2736575974"},"reference-count":45,"publisher":"MDPI AG","issue":"12","license":[{"start":{"date-parts":[[2020,11,30]],"date-time":"2020-11-30T00:00:00Z","timestamp":1606694400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Micromachines"],"abstract":"<jats:p>Current System-on-Chips (SoCs) execute applications with task dependency that compete for shared resources such as buses, memories, and accelerators. In such a structure, the arbitration policy becomes a critical part of the system to guarantee access and bandwidth suitable for the competing applications. Some strategies proposed in the literature to cope with these issues are Round-Robin, Weighted Round-Robin, Lottery, Time Division Access Multiplexing (TDMA), and combinations. However, a fine-grained bandwidth control arbitration policy is missing from the literature. We propose an innovative arbitration policy based on opportunistic access and a supervised utilization of the bus in terms of transmitted flits (transmission units) that settle the access and fine-grained control. In our proposal, every competing element has a budget. Opportunistic access grants the bus to request even if the component has spent all its flits. Supervised debt accounts a record for every transmitted flit when it has no flits to spend. Our proposal applies to interconnection systems such as buses, switches, and routers. The presented approach achieves deadlock-free behavior even with task dependency applications in the scenarios analyzed through cycle-accurate simulation models. The synergy between opportunistic and supervised debt techniques outperforms Lottery, TDMA, and Weighted Round-Robin in terms of bandwidth control in the experimental studies performed.<\/jats:p>","DOI":"10.3390\/mi11121063","type":"journal-article","created":{"date-parts":[[2020,11,30]],"date-time":"2020-11-30T10:26:12Z","timestamp":1606731972000},"page":"1063","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["A Bandwidth Control Arbitration for SoC Interconnections Performing Applications with Task Dependencies"],"prefix":"10.3390","volume":"11","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4009-7145","authenticated-orcid":false,"given":"Salvador","family":"Ibarra-Delgado","sequence":"first","affiliation":[{"name":"Center of Research, Innovation and Development in Telecommunications (CIDTE), Academic Unit of Electrical Engineering, Autonomous University of Zacatecas, Zacatecas 98000, Mexico"},{"name":"Department of Electronic and Computer Engineering, University of Cordoba, 14071 C\u00f3rdoba, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2129-5667","authenticated-orcid":false,"given":"Remberto","family":"Sandoval-Arechiga","sequence":"additional","affiliation":[{"name":"Center of Research, Innovation and Development in Telecommunications (CIDTE), Academic Unit of Electrical Engineering, Autonomous University of Zacatecas, Zacatecas 98000, Mexico"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2430-1484","authenticated-orcid":false,"given":"Jos\u00e9 Ricardo","family":"G\u00f3mez-Rodr\u00edguez","sequence":"additional","affiliation":[{"name":"Center of Research, Innovation and Development in Telecommunications (CIDTE), Academic Unit of Electrical Engineering, Autonomous University of Zacatecas, Zacatecas 98000, Mexico"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8312-1729","authenticated-orcid":false,"given":"Manuel","family":"Ort\u00edz-L\u00f3pez","sequence":"additional","affiliation":[{"name":"Department of Electronic and Computer Engineering, University of Cordoba, 14071 C\u00f3rdoba, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4002-3253","authenticated-orcid":false,"given":"Mar\u00eda","family":"Brox","sequence":"additional","affiliation":[{"name":"Department of Electronic and Computer Engineering, University of Cordoba, 14071 C\u00f3rdoba, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"1968","published-online":{"date-parts":[[2020,11,30]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Liu, W., Xu, J., Wu, X., Ye, Y., Wang, X., Zhang, W., Nikdast, M., and Wang, Z. (2011, January 4). A NoC Traffic Suite Based on Real Applications. Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI, Chennai, India.","DOI":"10.1109\/ISVLSI.2011.49"},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"189","DOI":"10.1023\/B:DAEM.0000003962.54165.5c","article-title":"Performance Analysis of Arbitration Policies for SoC Communication Architectures","volume":"8","author":"Poletti","year":"2003","journal-title":"Des. Autom. Embed. Syst."},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"261","DOI":"10.1049\/ip-cdt:20045100","article-title":"Network-on-chip architectures and design methods","volume":"152","author":"Benini","year":"2005","journal-title":"IEEE Proc. -Comput. Digit. Tech."},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"1842","DOI":"10.1109\/TVLSI.2017.2664660","article-title":"Overloaded CDMA crossbar for network-on-chip","volume":"25","author":"Ahmed","year":"2017","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"54","DOI":"10.1109\/MDAT.2017.2713352","article-title":"Formal-Based Design and Verification of SoC Arbitration Protocols: A Comparative Analysis of TDMA and Round-Robin","volume":"34","author":"Robbana","year":"2017","journal-title":"IEEE Des. Test"},{"key":"ref_6","unstructured":"Dally, W., and Towles, B. (2003). Principles and Practices of Interconnection Networks, Morgan Kaufmann Publishers Inc."},{"key":"ref_7","unstructured":"Agarwal, A., Iskander, C., and Shankar, R. (2009). Survey of network on chip (NoC) architectures & contributions. J. Eng. Comput. Archit., 3."},{"key":"ref_8","unstructured":"Quinton, S. (2019). A Bandwidth Reservation Mechanism for AXI-Based Hardware Accelerators on FPGAs. Proceedings of the 31st Euromicro Conference on Real-Time Systems (ECRTS 2019), Schloss Dagstuhl\u2013Leibniz-Zentrum fuer Informatik."},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1016\/j.micpro.2017.07.004","article-title":"Problems and challenges of emerging technology networks-on-chip: A review","volume":"53","year":"2017","journal-title":"Microprocess. Microsyst."},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"71","DOI":"10.1145\/1132952.1132953","article-title":"A survey of research and practices of network-on-chip","volume":"38","author":"Bjerregaard","year":"2006","journal-title":"ACM Comput. Surv."},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/2.976921","article-title":"Networks on chips: A new SoC paradigm","volume":"35","author":"Benini","year":"2002","journal-title":"Computer"},{"key":"ref_12","unstructured":"Wang, J., Li, Y., Peng, Q., and Tan, T. (2009, January 8\u201310). A dynamic priority arbiter for Network-on-Chip. Proceedings of the 2009 IEEE International Symposium on Industrial Embedded Systems, Lausanne, Switzerland."},{"key":"ref_13","unstructured":"Xilinx (2020, November 30). SmartConnect v1.0 LogiCOREo IP Product Guide, Vivado Design Suite, PG247. Available online: https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/smartconnect\/v1_0\/pg247-smartconnect.pdf."},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1049\/iet-cdt.2015.0049","article-title":"Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip","volume":"10","author":"Park","year":"2015","journal-title":"IET Comput. Digit. Tech."},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1049\/cje.2015.01.001","article-title":"An asynchronous adaptive priority round-robin arbiter based on four-phase dual-rail protocol","volume":"24","author":"Yang","year":"2015","journal-title":"Chin. J. Electron."},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"257","DOI":"10.1109\/TCAD.2017.2693263","article-title":"Classified Round Robin: A Simple Prioritized Arbitration to Equip Best Effort NoCs With Effective Hard QoS","volume":"37","author":"Rahmati","year":"2018","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"ref_17","doi-asserted-by":"crossref","unstructured":"Shah, H., Raabe, A., and Knoll, A. (2011, January 14\u201318). Priority division: A high-speed shared-memory bus arbitration with bounded latency. Proceedings of the 2011 Design, Automation Test in Europe, Grenoble, France.","DOI":"10.1109\/DATE.2011.5763319"},{"key":"ref_18","doi-asserted-by":"crossref","unstructured":"Chen, C.-H., Lee, G.-W., Huang, J.-D., and Jou, J.-Y. (2006, January 24\u201327). A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. Proceedings of the Asia and South Pacific Conference on Design Automation, Yokohama, Japan.","DOI":"10.1145\/1118299.1118441"},{"key":"ref_19","doi-asserted-by":"crossref","unstructured":"Lin, B., Lee, G., Huang, J., and Jou, J. (2007, January 23\u201326). A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. Proceedings of the 2007 Asia and South Pacific Design Automation Conference, okohama, Japan.","DOI":"10.1109\/ASPDAC.2007.357980"},{"key":"ref_20","doi-asserted-by":"crossref","unstructured":"Slijepcevic, M., Hernandez, C., Abella, J., and Cazorla, F.J. (2017). Design and implementation of a fair credit-based bandwidth sharing scheme for buses. Proceedings of the the 2017 Design, Automation and Test in Europe, Institute of Electrical and Electronics Engineers Inc.","DOI":"10.23919\/DATE.2017.7927122"},{"key":"ref_21","doi-asserted-by":"crossref","unstructured":"Li, H., Zhang, M., Zheng, W., and Li, D. (2007, January 5). An Adaptive Arbitration Algorithm for SoC Bus. Proceedings of the 2007 the International Conference on Networking, Architecture, and Storage (NAS 2007), Guilin, China.","DOI":"10.1109\/NAS.2007.9"},{"key":"ref_22","doi-asserted-by":"crossref","unstructured":"Akesson, B., Steffens, L., Strooisma, E., and Goossens, K. (2008, January 25\u201327). Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration. Proceedings of the 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Kaohsiung, Taiwan.","DOI":"10.1109\/RTCSA.2008.21"},{"key":"ref_23","doi-asserted-by":"crossref","unstructured":"Akesson, B., Steffens, L., and Goossens, K. (2009, January 5). Efficient Service Allocation in Hardware Using Credit-Controlled Static-Priority Arbitration. Proceedings of the 2009 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Beijing, China.","DOI":"10.1109\/RTCSA.2009.13"},{"key":"ref_24","doi-asserted-by":"crossref","unstructured":"Peng, H.K., and Lin, Y.L. (2010). An optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitration. ACM Trans. Embed. Comput. Syst., 9.","DOI":"10.1145\/1721695.1721701"},{"key":"ref_25","doi-asserted-by":"crossref","first-page":"20","DOI":"10.1109\/40.748793","article-title":"Designing and implementing a fast crossbar scheduler","volume":"19","author":"Gupta","year":"1999","journal-title":"IEEE Micro"},{"key":"ref_26","doi-asserted-by":"crossref","unstructured":"Shin, E.S., Mooney, V.J., and Riley, G.F. (2002, January 5). Round-robin Arbiter Design and Generation. Proceedings of the 15th International Symposium on System Synthesis, Kyoto, Japan.","DOI":"10.1145\/581250.581253"},{"key":"ref_27","doi-asserted-by":"crossref","first-page":"84","DOI":"10.1109\/TPDS.2007.253283","article-title":"Algorithm-hardware codesign of fast parallel round-robin arbiters","volume":"18","author":"Zheng","year":"2007","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"ref_28","doi-asserted-by":"crossref","unstructured":"Lee, Y.-L., Jou, J.M., and Chen, Y.-Y. (2009, January 5). A High-Speed and Decentralized Arbiter Design for NoC. Proceedings of the 2009 IEEE\/ACS International Conference on Computer Systems and Applications, Rabat, Morocco.","DOI":"10.1109\/AICCSA.2009.5069347"},{"key":"ref_29","doi-asserted-by":"crossref","unstructured":"Oveis-Gharan, M., and Khan, G.N. (2015, January 7\u201310). Index-based round-robin arbiter for NoC routers. Proceedings of the IEEE Computer Society Annual Symposium on VLSI, ISVLSI, Montpellier, France.","DOI":"10.1109\/ISVLSI.2015.27"},{"key":"ref_30","doi-asserted-by":"crossref","first-page":"81","DOI":"10.1016\/j.mejo.2017.03.004","article-title":"Ping-lock round robin arbiter","volume":"63","author":"Monemi","year":"2017","journal-title":"Microelectron. J."},{"key":"ref_31","doi-asserted-by":"crossref","unstructured":"Xu, Y., Li, L., Gao, M., Zhang, B., Jiang, Z., Du, G., and Zhang, W. (2006, January 8). An Adaptive Dynamic Arbiter for Multi-Processor SoC. Proceedings of the 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China.","DOI":"10.1109\/ICSICT.2006.306551"},{"key":"ref_32","doi-asserted-by":"crossref","unstructured":"Jun, M., Bang, K., Lee, H., Chang, N., and Chung, E. (2007, January 23\u201326). Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems. Proceedings of the 2007 Asia and South Pacific Design Automation Conference, Yokohama, Japan.","DOI":"10.1109\/ASPDAC.2007.357979"},{"key":"ref_33","doi-asserted-by":"crossref","unstructured":"Lara, E., Debon, G., Goerl, R., Villa, P., Schramm, D., Poehls, L.B., and Vargas, F. (2019, January 11\u201313). A New Approach to Guarantee Critical Task Schedulability in TDMA-Based Bus Access of Multicore Architecture. Proceedings of the 2019 IEEE Latin American Test Symposium (LATS), Santiago, Chile.","DOI":"10.1109\/LATW.2019.8704572"},{"key":"ref_34","doi-asserted-by":"crossref","first-page":"818","DOI":"10.1109\/TVLSI.2009.2015665","article-title":"Implementation of a self-motivated arbitration scheme for the multilayer AHB busmatrix","volume":"18","author":"Hwang","year":"2010","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_35","doi-asserted-by":"crossref","unstructured":"Sousa, E., Gangadharan, D., Hannig, F., and Teich, J. (2014, January 7). Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures. Proceedings of the 17th Euromicro Conference on Digital System Design, Verona, Italy.","DOI":"10.1109\/DSD.2014.105"},{"key":"ref_36","doi-asserted-by":"crossref","unstructured":"Xu, Z., Zhang, S., Ni, W., Yang, Y., and Bu, J. (2014, January 5). Design and implementation of a dynamic weight arbiter for networks-on-chip. Proceedings of the ICIST 2014\u2014Proceedings of 2014 4th IEEE International Conference on Information Science and Technology, Shenzhen, China.","DOI":"10.1109\/ICIST.2014.6920401"},{"key":"ref_37","first-page":"113","article-title":"A Bus Arbitration Scheme with an Efficient Utilization and Distribution","volume":"8","author":"Amin","year":"2017","journal-title":"Int. J. Adv. Comput. Sci. Appl."},{"key":"ref_38","doi-asserted-by":"crossref","unstructured":"Richardson, T.D., Nicopoulos, C., Park, D., Narayanan, V., Xie, Y., Das, C., and Degalahal, V. (2006, January 7). A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks. Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID\u201906), Hyderabad, India.","DOI":"10.1109\/VLSID.2006.10"},{"key":"ref_39","doi-asserted-by":"crossref","unstructured":"Burgio, P., Ruggiero, M., Esposito, F., Marinoni, M., Buttazzo, G., and Benini, L. (2010, January 10). Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systems. Proceedings of the 2010 IEEE International Conference on Computer Design, Qinhuangdao, China.","DOI":"10.1109\/ICCD.2010.5647792"},{"key":"ref_40","doi-asserted-by":"crossref","unstructured":"Lee, M.M., Kim, J., Abts, D., and Lee, J.W. (2010, January 6). Approximating Age-Based Arbitration in On-Chip Networks. Proceedings of the 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), Vienna Austria.","DOI":"10.1145\/1854273.1854359"},{"key":"ref_41","doi-asserted-by":"crossref","first-page":"596","DOI":"10.1109\/TVLSI.2006.878210","article-title":"The LOTTERYBUS on-chip communication architecture","volume":"14","author":"Lahiri","year":"2006","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_42","doi-asserted-by":"crossref","first-page":"443","DOI":"10.1016\/j.sysarc.2019.01.013","article-title":"A new approach to the Population-Based Incremental Learning algorithm using virtual regions for task mapping on NoCs","volume":"97","author":"Bagherzadeh","year":"2019","journal-title":"J. Syst. Archit."},{"key":"ref_43","doi-asserted-by":"crossref","unstructured":"Sandoval-Arechiga, R., Vazquez-Avila, J.L., Parra-Michel, R., Flores-Troncoso, J., and Ibarra-Delgado, S. (2015, January 5). Shifting the Network-on-Chip Paradigm towards a Software Defined Network Architecture. Proceedings of the 2015 International Conference on Computational Science and Computational Intelligence (CSCI), Las Vegas, NV, USA.","DOI":"10.1109\/CSCI.2015.45"},{"key":"ref_44","doi-asserted-by":"crossref","unstructured":"Restuccia, F., Pagani, M., Biondi, A., Marinoni, M., and Buttazzo, G. (2019). Is your bus arbiter really fair? Restoring fairness in axi interconnects for FPGA SOCs. ACM Trans. Embed. Comput. Syst., 18.","DOI":"10.1145\/3358183"},{"key":"ref_45","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1109\/TCAD.2008.2010691","article-title":"Outstanding research problems in NoC design: System, microarchitecture, and circuit perspectives","volume":"28","author":"Marculescu","year":"2009","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."}],"container-title":["Micromachines"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2072-666X\/11\/12\/1063\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T10:39:34Z","timestamp":1760179174000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2072-666X\/11\/12\/1063"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,30]]},"references-count":45,"journal-issue":{"issue":"12","published-online":{"date-parts":[[2020,12]]}},"alternative-id":["mi11121063"],"URL":"https:\/\/doi.org\/10.3390\/mi11121063","relation":{},"ISSN":["2072-666X"],"issn-type":[{"value":"2072-666X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,11,30]]}}}