{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,25]],"date-time":"2026-06-25T16:58:28Z","timestamp":1782406708340,"version":"3.54.5"},"reference-count":46,"publisher":"MDPI AG","issue":"3","license":[{"start":{"date-parts":[[2023,2,21]],"date-time":"2023-02-21T00:00:00Z","timestamp":1676937600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"Hainan University project funding","award":["KYQD (ZR)1974"],"award-info":[{"award-number":["KYQD (ZR)1974"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Micromachines"],"abstract":"<jats:p>Hundreds of processor cores or modules are integrated into a single chip. The traditional bus or crossbar is challenged by bandwidth, scalability, and silicon area, and cannot meet the requirements of high end applications. Network-on-chip (NoC) has become a very promising interconnection structure because of its good scalability, predictable interconnect length and delay, high bandwidth, and reusability. However, the most available packet routing NoC may not be the perfect solution for high-end heterogeneous multi-core real-time systems-on-chip (SoC) because of the excessive latency and cache cost overhead. Moreover, circuit switching is limited by the scale, connectivity flexibility, and excessive overhead of fully connected systems. To solve the above problems and to meet the need for low latency, high throughput, and flexibility, this paper proposes PCCNoC (Packet Connected Circuit NoC), a low-latency and low-overhead NoC based on both packet switching (setting-up circuit) and circuit switching (data transmission on circuit), which offers flexible routing and zero overhead of data transmission latency, making it suitable for high-end heterogeneous multi-core real-time SoC at various system scales. Compared with typically available packet switched NoC, our PCCoC sees 242% improved performance and 97% latency reduction while keeping the silicon cost relatively low.<\/jats:p>","DOI":"10.3390\/mi14030501","type":"journal-article","created":{"date-parts":[[2023,2,22]],"date-time":"2023-02-22T03:32:17Z","timestamp":1677036737000},"page":"501","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":8,"title":["PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs"],"prefix":"10.3390","volume":"14","author":[{"given":"Xinbing","family":"Zhou","sequence":"first","affiliation":[{"name":"School of Information and Communication Engineering, Hainan University, Haikou 570228, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Peng","family":"Hao","sequence":"additional","affiliation":[{"name":"School of Computer Science, Northwestern Polytechnical University, Xi\u2019an 710072, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dake","family":"Liu","sequence":"additional","affiliation":[{"name":"School of Information and Communication Engineering, Hainan University, Haikou 570228, China"},{"name":"Ultichip Communications Technology Company Limited, Beijing 100191, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"1968","published-online":{"date-parts":[[2023,2,21]]},"reference":[{"key":"ref_1","unstructured":"Bennett, H. (2023, February 12). International Technology Roadmap for Semiconductors 2015 Edition Outside System Connectivity, Available online: https:\/\/www.nist.gov\/publications\/international-technology-roadmap-semiconductors-2015-edition-outside-system."},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"304","DOI":"10.1016\/j.micpro.2013.09.006","article-title":"Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip","volume":"38","author":"Wang","year":"2014","journal-title":"Microprocess. Microsyst."},{"key":"ref_3","unstructured":"Balasubramonian, R., and Pinkston, T.M. (2011). Buses and Crossbars, Springer."},{"key":"ref_4","first-page":"1216","article-title":"Networks on chip","volume":"57","author":"Jantsch","year":"2010","journal-title":"IEEE Trans. Comput."},{"key":"ref_5","unstructured":"Dally, W.J., and Towles, B.P. (2004). Principles and Practices of Interconnection Networks, Elsevier."},{"key":"ref_6","doi-asserted-by":"crossref","unstructured":"Liu, S., Jantsch, A., and Lu, Z. (2013, January 4\u20136). Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC. Proceedings of the 2013 Euromicro Conference on Digital System Design, Los Alamitos, CA, USA.","DOI":"10.1109\/DSD.2013.13"},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"100333","DOI":"10.1016\/j.nancom.2020.100333","article-title":"VCS: A Method of In-order Packet Delivery for Adaptive NoC Routing","volume":"28","author":"Das","year":"2020","journal-title":"Nano Commun. Netw."},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"163","DOI":"10.1109\/TPDS.2022.3217296","article-title":"MRCN: Throughput-Oriented Multicast Routing for Customized Network-on-Chips","volume":"34","author":"Lee","year":"2022","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"168783","DOI":"10.1109\/ACCESS.2021.3137218","article-title":"MRBS: An Area-Efficient Multicast Router for Network-on-Chip Using Buffer Sharing","volume":"9","author":"Yang","year":"2021","journal-title":"IEEE Access"},{"key":"ref_10","doi-asserted-by":"crossref","unstructured":"Anjali, N., and Somasundaram, K. (2014, January 13\u201314). Design and evaluation of virtual channel router for mesh-of-grid based NoC. Proceedings of the 2014 International Conference on Electronics and Communication Systems (ICECS), Coimbatore, India.","DOI":"10.1109\/ECS.2014.6892817"},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"60","DOI":"10.1016\/j.micpro.2017.08.007","article-title":"ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform","volume":"54","author":"Monemi","year":"2017","journal-title":"Microprocess. Microsyst."},{"key":"ref_12","doi-asserted-by":"crossref","unstructured":"Gonz\u00e1lez, Y.R., Nelissen, G., and Tovar, E. (2022, January 23\u201325). IPDeN: Real-Time deflection-based NoC with in-order flits delivery. Proceedings of the 2022 IEEE 28th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Taipei, Taiwan.","DOI":"10.1109\/RTCSA55878.2022.00023"},{"key":"ref_13","doi-asserted-by":"crossref","unstructured":"Tobuschat, S., Axer, P., Ernst, R., and Diemer, J. (2013, January 19\u201321). IDAMC: A NoC for mixed criticality systems. Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, Taipei, Taiwan.","DOI":"10.1109\/RTCSA.2013.6732214"},{"key":"ref_14","doi-asserted-by":"crossref","unstructured":"Konstantinou, D., Nicopoulos, C., Lee, J., Sirakoulis, G.C., and Dimitrakopoulos, G. (2020, January 12\u201314). SmartFork: Partitioned multicast allocation and switching in network-on-chip routers. Proceedings of the 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain.","DOI":"10.1109\/ISCAS45731.2020.9180774"},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"730","DOI":"10.1007\/s10766-019-00648-9","article-title":"DancerFly: An Order-Aware Network-on-Chip Router On-the-Fly Mitigating Multi-path Packet Reordering","volume":"48","author":"Jin","year":"2020","journal-title":"Int. J. Parallel Program."},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"386","DOI":"10.1016\/j.compeleceng.2014.12.009","article-title":"The Hamiltonian-based odd-even turn model for maximally adaptive routing in 2D mesh networks-on-chip","volume":"45","author":"Bahrebar","year":"2015","journal-title":"Comput. Electr. Eng."},{"key":"ref_17","doi-asserted-by":"crossref","unstructured":"Liu, D. (2008). Embedded DSP Processor Design: Application Specific Instruction Set Processors, Elsevier.","DOI":"10.1016\/B978-012374123-3.50011-7"},{"key":"ref_18","doi-asserted-by":"crossref","unstructured":"Das, T.S., Ghosal, P., and Chatterjee, N. (2019, January 13). Virtual circuit switch based orderly delivery of packets in adaptive noc routing. Proceedings of the 12th International Workshop on Network on Chip Architectures, Columbus, OH, USA.","DOI":"10.1145\/3356045.3360719"},{"key":"ref_19","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3356235","article-title":"Smart-hop arbitration request propagation: Avoiding quadratic arbitration complexity and false negatives in SMART NoCs","volume":"24","author":"Asgarieh","year":"2019","journal-title":"ACM Trans. Des. Autom. Electron. Syst. (TODAES)"},{"key":"ref_20","doi-asserted-by":"crossref","unstructured":"Zheng, H., Wang, K., and Louri, A. (March, January 27). Adapt-noc: A flexible network-on-chip design for heterogeneous manycore architectures. Proceedings of the 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, Republic of Korea.","DOI":"10.1109\/HPCA51647.2021.00066"},{"key":"ref_21","doi-asserted-by":"crossref","unstructured":"Kwon, H., and Krishna, T. (2017, January 24\u201325). OpenSMART: Single-cycle multi-hop NoC generator in BSV and Chisel. Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Santa Rosa, CA, USA.","DOI":"10.1109\/ISPASS.2017.7975291"},{"key":"ref_22","doi-asserted-by":"crossref","unstructured":"Farrokhbakht, H., Gratz, P.V., Krishna, T., San Miguel, J., and Jerger, N.E. (2022, January 2\u20136). Stay in your Lane: A NoC with Low-overhead Multi-packet Bypassing. Proceedings of the 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, Republic of Korea.","DOI":"10.1109\/HPCA53966.2022.00074"},{"key":"ref_23","doi-asserted-by":"crossref","unstructured":"Ejaz, A., and Sourdis, I. (2022, January 2\u20136). FastTrackNoC: A NoC with FastTrack Router Datapaths. Proceedings of the 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, Republic of Korea.","DOI":"10.1109\/HPCA53966.2022.00075"},{"key":"ref_24","doi-asserted-by":"crossref","unstructured":"Stensgaard, M.B., and Spars\u00f8, J. (2008, January 7\u201310). Renoc: A network-on-chip architecture with reconfigurable topology. Proceedings of the Second ACM\/IEEE International Symposium on Networks-on-Chip (nocs 2008), Newcastle upon Tyne, UK.","DOI":"10.1109\/NOCS.2008.4492725"},{"key":"ref_25","first-page":"583","article-title":"daelite: A tdm noc supporting qos, multicast, and fast connection set-up","volume":"63","author":"Stefan","year":"2012","journal-title":"IEEE Trans. Comput."},{"key":"ref_26","doi-asserted-by":"crossref","first-page":"414","DOI":"10.1109\/MDT.2005.99","article-title":"\u00c6thereal network on chip: Concepts, architectures, and implementations","volume":"22","author":"Goossens","year":"2005","journal-title":"IEEE Des. Test Comput."},{"key":"ref_27","doi-asserted-by":"crossref","first-page":"2010","DOI":"10.1109\/TVLSI.2010.2066586","article-title":"Application-aware topology reconfiguration for on-chip networks","volume":"19","author":"Modarressi","year":"2010","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_28","doi-asserted-by":"crossref","unstructured":"Kim, M.M., Davis, J.D., Oskin, M., and Austin, T. (2008, January 21\u201325). Polymorphic on-chip networks. Proceedings of the 2008 International Symposium on Computer Architecture, Beijing, China.","DOI":"10.1109\/ISCA.2008.25"},{"key":"ref_29","doi-asserted-by":"crossref","unstructured":"Papamichael, M.K., and Hoe, J.C. (2012, January 22\u201324). CONNECT: Re-examining conventional wisdom for designing NoCs in the context of FPGAs. Proceedings of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, USA.","DOI":"10.1145\/2145694.2145703"},{"key":"ref_30","doi-asserted-by":"crossref","first-page":"217","DOI":"10.1016\/j.micpro.2010.10.003","article-title":"System design of full HD MVC decoding on mesh-based multicore NoCs","volume":"35","author":"Ma","year":"2011","journal-title":"Microprocess. Microsyst."},{"key":"ref_31","doi-asserted-by":"crossref","unstructured":"Lusala, A.K., and Legat, J.D. (2011, January 15\u201318). Combining sdm-based circuit switching with packet switching in a NoC for real-time applications. Proceedings of the IEEE International Symposium of Circuits and Systems, Rio de Janeiro, Brazil.","DOI":"10.1109\/ISCAS.2011.5938113"},{"key":"ref_32","doi-asserted-by":"crossref","unstructured":"Jerger, N., Peh, L.S., and Lipasti, M.H. (2008, January 7\u201310). Circuit-Switched Coherence. Proceedings of the Second ACM\/IEEE International Symposium on Networks-on-Chip (nocs 2008), Newcastle upon Tyne, UK.","DOI":"10.1109\/NOCS.2008.4492738"},{"key":"ref_33","doi-asserted-by":"crossref","unstructured":"Mazloumi, A., and Modarressi, M. (2015, January 9\u201313). A hybrid packet\/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors. Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France.","DOI":"10.7873\/DATE.2015.0944"},{"key":"ref_34","unstructured":"Yong, C., Matus, E., and Fettweis, G.P. (2017, January 18\u201331). Combined packet and TDM circuit switching NoCs with novel connection configuration mechanism. Proceedings of the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA."},{"key":"ref_35","unstructured":"Fallahrad, M., Patooghy, A., Ziaeeziabari, H., and Taheri, E. (September, January 31). CirKet: A Performance Efficient Hybrid Switching Mechanism for NoC Architectures. Proceedings of the Digital System Design, Limassol, Cyprus."},{"key":"ref_36","doi-asserted-by":"crossref","unstructured":"Modarressi, M., Sarbaziazad, H., and Arjoma, M. (2009, January 20\u201324). A hybrid packet-circuit switched on-chip network based on SDM. Proceedings of the 2009 Design, Automation & Test in Europe Conference & Exhibition, Nice, France.","DOI":"10.1109\/DATE.2009.5090728"},{"key":"ref_37","doi-asserted-by":"crossref","unstructured":"Zeng, S.M., Ni, W., Zhang, Y.X., Song, Y.K., and Zhang, D.L. (2022, January 25\u201328). Design of adaptive transmission NoC based on packet and circuit switching mechanism. Proceedings of the 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), Nanjing, China.","DOI":"10.1109\/ICSICT55466.2022.9963398"},{"key":"ref_38","doi-asserted-by":"crossref","first-page":"1044","DOI":"10.1109\/TPDS.2017.2783337","article-title":"Efficient Timing Channel Protection for Hybrid (Packet\/Circuit-Switched) Network-on-Chip","volume":"29","author":"Biswas","year":"2018","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"ref_39","doi-asserted-by":"crossref","first-page":"104551","DOI":"10.1016\/j.micpro.2022.104551","article-title":"PAAD (Partially adaptive and deterministic routing): A Deadlock Free Congestion Aware Hybrid Routing for 2D Mesh Network-on-chips","volume":"92","author":"Manzoor","year":"2022","journal-title":"Microprocess. Microsyst."},{"key":"ref_40","doi-asserted-by":"crossref","unstructured":"Catania, V., Mineo, A., Monteleone, S., Palesi, M., and Patti, D. (2015, January 27\u201329). Noxim: An open, extensible and cycle-accurate network on chip simulator. Proceedings of the 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Toronto, ON, Canada.","DOI":"10.1109\/ASAP.2015.7245728"},{"key":"ref_41","unstructured":"Soteriou, V., Wang, H., and Peh, L. (2006, January 11\u201314). A statistical traffic model for on-chip interconnection networks. Proceedings of the 14th IEEE International Symposium on Modeling, Analysis, and Simulation, Monterey, CA, USA."},{"key":"ref_42","doi-asserted-by":"crossref","first-page":"1495","DOI":"10.1109\/TCAD.2015.2413848","article-title":"Fault-tolerant topology generation method for application-specific network-on-chips","volume":"34","author":"Tosun","year":"2015","journal-title":"IEEE Trans.-Comput.-Aided Des. Integr. Syst."},{"key":"ref_43","doi-asserted-by":"crossref","first-page":"639","DOI":"10.1109\/92.902258","article-title":"The interpretation and application of Rent\u2019s rule","volume":"8","author":"Christie","year":"2000","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_44","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2629677","article-title":"An evaluation of high-level mechanistic core models","volume":"11","author":"Carlson","year":"2014","journal-title":"ACM Trans. Archit. Code Optim. (TACO)"},{"key":"ref_45","doi-asserted-by":"crossref","unstructured":"Bienia, C., Kumar, S., Singh, J.P., and Li, K. (2008, January 25\u201329). The PARSEC benchmark suite: Characterization and architectural implications. Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, Toronto, ON, Canada.","DOI":"10.1145\/1454115.1454128"},{"key":"ref_46","doi-asserted-by":"crossref","first-page":"511","DOI":"10.1109\/TVLSI.2018.2879675","article-title":"A high-flexible low-latency memory-based FFT processor for 4G, WLAN, and future 5G","volume":"27","author":"Liu","year":"2018","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."}],"container-title":["Micromachines"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2072-666X\/14\/3\/501\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,10]],"date-time":"2025-10-10T18:38:15Z","timestamp":1760121495000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2072-666X\/14\/3\/501"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,2,21]]},"references-count":46,"journal-issue":{"issue":"3","published-online":{"date-parts":[[2023,3]]}},"alternative-id":["mi14030501"],"URL":"https:\/\/doi.org\/10.3390\/mi14030501","relation":{},"ISSN":["2072-666X"],"issn-type":[{"value":"2072-666X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,2,21]]}}}