{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,27]],"date-time":"2026-08-27T15:27:42Z","timestamp":1787844462354,"version":"build-2784847793"},"reference-count":25,"publisher":"MDPI AG","issue":"9","license":[{"start":{"date-parts":[[2023,8,22]],"date-time":"2023-08-22T00:00:00Z","timestamp":1692662400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"faculty research fund of Sejong University"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Micromachines"],"abstract":"<jats:p>In this article, a novel statistical approach is proposed and applied to co-design signal and power integrity (SI\/PI) in high-speed interconnects considering the non-linear power\/ground noise generated by parallel buffers and bit-patterns. With increased data rates and decreased operating voltages, the allowed noise margin in high-speed interconnects is continuously reduced, and this trend requires SI\/PI co-design. Specifically, non-linear power\/ground noise associated with simultaneous switching circuits sharing a power delivery network (PDN) and bit-patterns must be carefully considered during the interconnects\u2019 design and analysis phase. In many cases, conventional electromagnetic (EM) and transient circuit simulators require heavy computational resources or even fail to deliver an accurate result. The proposed statistical method estimates the statistical eye-diagram in the high-speed interconnect considering power\/ground noise and bit-patterns such as data bus inversion (DBI) coding. The accuracy and computational efficiency of the proposed method are validated by comparing the result with HSPICE transient simulation result. The proposed method is also compared with conventional statistical methods, such as peak distortion analysis (PDA) and statistical channel simulation in the transient simulator. Lastly, the proposed method is applied to the SI\/PI co-design and co-analysis in the high bandwidth memory (HBM) interposer channel. Impacts of decoupling capacitors on hierarchical PDN impedance, statistical eye-diagram of the HBM channel, and bit error rate (BER) Bathtub curves are summarized. Finally, the BER eye-diagram is derived from the estimated statistical eye-diagram for timing and voltage analysis. The impacts of hierarchical PDN design and bit-patterns on SI\/PI are discussed.<\/jats:p>","DOI":"10.3390\/mi14091654","type":"journal-article","created":{"date-parts":[[2023,8,23]],"date-time":"2023-08-23T07:25:24Z","timestamp":1692775524000},"page":"1654","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["A Statistical Approach for Signal and Power Integrity Co-Design in High-Speed Interconnects Considering Non-Linear Power\/Ground Noise and Bit-Patterns"],"prefix":"10.3390","volume":"14","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0096-2296","authenticated-orcid":false,"given":"Youngwoo","family":"Kim","sequence":"first","affiliation":[{"name":"Department of Semiconductor System Engineering, Sejong University, Seoul 05006, Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"1968","published-online":{"date-parts":[[2023,8,22]]},"reference":[{"key":"ref_1","unstructured":"(2015). High Bandwidth Memory (HBM) DRAM (Standard No. JESD235A)."},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"1658","DOI":"10.1109\/TCPMT.2017.2779838","article-title":"Signal Integrity Design and Analysis of Silicon Interposer for GPU-Memory Channels in High-Bandwidth Memory Interface","volume":"8","author":"Cho","year":"2018","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"107","DOI":"10.1109\/TCPMT.2018.2843442","article-title":"Signal Integrity Design and Analysis of Differential High-Speed Serial Links in Silicon Interposer With Through-Silicon Via","volume":"9","author":"Cho","year":"2018","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_4","unstructured":"SK Hynix (2016). High Bandwidth Roadmap, SK Hynix."},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"1835","DOI":"10.1109\/TCPMT.2019.2895083","article-title":"Fast and Accurate Power Distribution Network (PDN) Modeling of A Silicon Interposer for 2.5-D\/3-D ICs with Multi-array TSVs","volume":"9","author":"Cho","year":"2019","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"1747","DOI":"10.1109\/TEMC.2016.2587824","article-title":"Measurement and Analysis of Glass Interposer Power Distribution Network Resonance Effects on a High-Speed Through Glass via Channel","volume":"58","author":"Kim","year":"2016","journal-title":"IEEE Trans. Electromagn. Compat."},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Kim, H., Lee, S., Song, K., Shin, Y., Park, D., Park, J., Cho, J., and Ahn, S. (2022). A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory. Micromachines, 13.","DOI":"10.3390\/mi13071070"},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"392","DOI":"10.1109\/TEMC.2010.2045381","article-title":"Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions","volume":"52","author":"Fan","year":"2010","journal-title":"IEEE Trans. Electromagn. Compat."},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"1585","DOI":"10.1109\/TEMC.2014.2315837","article-title":"Closed-Form Expressions for the Noise Voltage Caused by a Burst Train of IC Switching Currents on a Power Distribution Network","volume":"56","author":"Kim","year":"2014","journal-title":"IEEE Trans. Electromagn. Compat."},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"113","DOI":"10.1109\/TCPMT.2012.2226723","article-title":"Analytical Transfer Functions Relating Power and Ground Voltage Fluctuations to Jitter at a Single-Ended Full-Swing Buffer","volume":"3","author":"Hwang","year":"2012","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"2022","DOI":"10.1109\/TCSI.2013.2295933","article-title":"Analytical Probability Density Calculation for Step Pulse Response of a Single-Ended Buffer With Arbitrary Power-Supply Voltage Fluctuations","volume":"61","author":"Kim","year":"2014","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_12","unstructured":"Casper, B.K., Haycock, M., and Mooney, R. (2002, January 13\u201315). An accurate and efficient analysis method for multi-Gb\/s chip-to-chip signaling schemes. Proceedings of the 2002 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, USA."},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"927","DOI":"10.1109\/TEMC.2016.2630080","article-title":"An Efficient Crosstalk-Included Eye-Diagram Estimation Method for High-Speed Interposer Channel on 2.5-D and 3-D IC","volume":"59","author":"Choi","year":"2016","journal-title":"IEEE Trans. Electromagn. Compat."},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"1510","DOI":"10.1109\/TEMC.2017.2766295","article-title":"A Novel Stochastic Model-Based Eye-Diagram Estimation Method for 8B\/10B and TMDS-Encoded High-Speed Channels","volume":"60","author":"Park","year":"2017","journal-title":"IEEE Trans. Electromagn. Compat."},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"1198","DOI":"10.1109\/TEMC.2018.2843813","article-title":"A Novel Eye-diagram Estimation Method for Pulse Amplitude Modulation with N-Level (PAM-N) on Stacked Through-Silicon Vias (TSVs)","volume":"61","author":"Park","year":"2018","journal-title":"IEEE Trans. Electromagn. Compat."},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"1655","DOI":"10.1109\/TEMC.2015.2457928","article-title":"Estimation method for statistical eye-diagram in a non-linear digital channel","volume":"57","author":"Chou","year":"2015","journal-title":"IEEE Trans. Electro-Magn. Compat."},{"key":"ref_17","doi-asserted-by":"crossref","first-page":"741","DOI":"10.1109\/TADVP.2008.2002201","article-title":"Multiple Edge Responses for Fast and Accurate System Simulations","volume":"31","author":"Oh","year":"2008","journal-title":"IEEE Trans. Adv. Packag."},{"key":"ref_18","unstructured":"Oh, D., and Yuan, X. (2012). High-Speed Signaling: Jitter Modeling, Analysis and Budgeting, Prentice Hall. [1st ed.]."},{"key":"ref_19","unstructured":"Kim, K. (2015). Fast and Analytical Eye Diagram Estimation Method for High Bandwidth Memory (HBM) Channel Including Tx Power Noise and Channel Crosstalk. [Ph.D. Dissertation, KAIST]."},{"key":"ref_20","doi-asserted-by":"crossref","unstructured":"Kim, J. (2015, January 14\u201316). Analytical Calculation of Pattern-Dependent Simultaneous Switching Outputs (SSO) due to Power Supply Fluctuations. Proceedings of the 2015 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), Seoul, Republic of Korea.","DOI":"10.1109\/EDAPS.2015.7383716"},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"156","DOI":"10.1109\/TCSI.2016.2611009","article-title":"Statistical Analysis for Patter-Dependent Simultaneous Switching Outputs (SSO) of Parallel Single-Ended Buffers","volume":"64","author":"Kim","year":"2017","journal-title":"IEEE Trans. Circuits Syst.-1 Regul. Pap."},{"key":"ref_22","doi-asserted-by":"crossref","unstructured":"Kim, Y., Fujimoto, D., Nishiyama, H., Hayashi, Y.-I., Lho, D., Park, H., and Kim, J. (2019, January 21\u201323). Statistical Analysis of Simultaneous Switching Output (SSO) Impacts on Steady State Output Responses and Signal Integrity. Proceedings of the 2019 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo), Hangzhou, China.","DOI":"10.1109\/EMCCompo.2019.8919652"},{"key":"ref_23","doi-asserted-by":"crossref","first-page":"170","DOI":"10.1587\/nolta.11.170","article-title":"Segmentation method based modeling and analysis of a glass package power distribution network (PDN)","volume":"11","author":"Kim","year":"2020","journal-title":"Nonlinear Theory Its Appl. IEICE"},{"key":"ref_24","doi-asserted-by":"crossref","unstructured":"Cho, K., Kim, Y., Kim, S., Lee, H., Choi, S., Kim, H., and Kim, J. (2016, January 27). Power Distribution Network (PDN) Design and Analysis of A Single and Double-Sided High Bandwidth Memory (HBM) Interposer for 2.5D Terabtye\/s Bandwidth System. Proceedings of the IEEE International Conference on Signal and Power Integrity (SIPI 2016) An embedded conference within the IEEE International Symposium on Electromagnetic Compatibility, Ottawa, ON, Canada.","DOI":"10.1109\/ISEMC.2016.7571620"},{"key":"ref_25","doi-asserted-by":"crossref","first-page":"467","DOI":"10.1109\/TCPMT.2020.2972019","article-title":"Deep Reinforcement Learning-Based Optimal Decoupling Capacitor Design Method for Silicon Interposer-Based 2.5-D\/3-D ICs","volume":"10","author":"Park","year":"2020","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."}],"container-title":["Micromachines"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2072-666X\/14\/9\/1654\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,10]],"date-time":"2025-10-10T20:39:50Z","timestamp":1760128790000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2072-666X\/14\/9\/1654"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,8,22]]},"references-count":25,"journal-issue":{"issue":"9","published-online":{"date-parts":[[2023,9]]}},"alternative-id":["mi14091654"],"URL":"https:\/\/doi.org\/10.3390\/mi14091654","relation":{},"ISSN":["2072-666X"],"issn-type":[{"value":"2072-666X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,8,22]]}}}