{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,10]],"date-time":"2025-10-10T01:02:32Z","timestamp":1760058152089,"version":"build-2065373602"},"reference-count":37,"publisher":"MDPI AG","issue":"3","license":[{"start":{"date-parts":[[2025,3,13]],"date-time":"2025-03-13T00:00:00Z","timestamp":1741824000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Micromachines"],"abstract":"<jats:p>This paper reviews recent developments in highly integrated all-digital frequency synthesizers suitable to deploy in low-power internet-of-things (IoT) applications. This review sets low power consumption as a key criterion for exploring the all-digital frequency synthesizer implemented in CMOS fabrication technology. The alignment with mainstream CMOS technology offers high-density, comprehensive, robust signal processing capability, making it very suitable for all-digital phase-locked loops to harvest that capacity, and it becomes inevitable. This review includes various divider-less low-power frequency synthesizers, including all-digital phase-locked loops (ADPLL), all-digital frequency-locked loops (ADFLL), and hybrid PLLs. This paper also discusses the latest architectural developments for ADPLLs to lead to low-power implementation, such as DTC-assisted TDC, embedded TDC, and various levels of hybridization in ADPLLs.<\/jats:p>","DOI":"10.3390\/mi16030333","type":"journal-article","created":{"date-parts":[[2025,3,13]],"date-time":"2025-03-13T04:18:32Z","timestamp":1741839512000},"page":"333","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A Review on Micro-Watts All-Digital Frequency Synthesizers"],"prefix":"10.3390","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3856-6304","authenticated-orcid":false,"given":"Venkadasamy","family":"Navaneethan","sequence":"first","affiliation":[{"name":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore"},{"name":"CM Engineering Labs Singapore Pte. Ltd., Singapore 608526, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5834-5640","authenticated-orcid":false,"given":"Boon Chiat Terence","family":"Teo","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore"},{"name":"Silicon Laboratories International Pte. Ltd., Singapore 539775, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Annamalai Arasu","family":"Muthukumaraswamy","sequence":"additional","affiliation":[{"name":"CM Engineering Labs Singapore Pte. Ltd., Singapore 608526, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6427-4316","authenticated-orcid":false,"given":"Xian Yang","family":"Lim","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore"},{"name":"Analog Devices Singapore, Singapore 349248, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0415-6497","authenticated-orcid":false,"given":"Liter","family":"Siek","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2025,3,13]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Kim, J. (2015, January 31). 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