{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T10:25:00Z","timestamp":1775039100516,"version":"3.50.1"},"reference-count":22,"publisher":"MDPI AG","issue":"4","license":[{"start":{"date-parts":[[2026,3,31]],"date-time":"2026-03-31T00:00:00Z","timestamp":1774915200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"MACHAME"},{"DOI":"10.13039\/501100002347","name":"Bundesministerium f\u00fcr Forschung, Technologie und Raumfahrt","doi-asserted-by":"publisher","award":["16ME0908K"],"award-info":[{"award-number":["16ME0908K"]}],"id":[{"id":"10.13039\/501100002347","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Merck KGaA and Infineon Technologies AG"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Micromachines"],"abstract":"<jats:p>Memristor-based configuration memory offers an alternative solution to the volatility and large area overhead of conventional Static Random Access Memory (SRAM)-based FPGA configuration memory. Their non-volatile nature and the possibility of stacking them on top of the logic layer in a process called Back-End-Of-Line (BEOL) manufacturing help not only dramatically reduce area consumption but also significantly reduce startup time. However, due to the comparatively high defect probability caused by manufacturing defects, traditional approaches for defect tolerance are not fit to address these defects. This work introduces an approach to defect-aware and tolerant synthesis. Based on this, an investigation into the defect tolerance of different architecture choices regarding the size of LUTs and the fracturability of LUTs is presented. We can show that smaller, non-fracturable LUTs exhibit a higher defect tolerance. Moreover, multiple strategies to improve the mapping result based on the properties of the logic functions are introduced. Notably, reducing the mapping complexity of logic clusters during the packing stage significantly improves the mapping success rate.<\/jats:p>","DOI":"10.3390\/mi17040429","type":"journal-article","created":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T08:08:34Z","timestamp":1775030914000},"page":"429","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Impact of Fabrication Defects on FPGA Logic Using Memristor-Based Memory Cells"],"prefix":"10.3390","volume":"17","author":[{"ORCID":"https:\/\/orcid.org\/0009-0007-6369-5136","authenticated-orcid":false,"given":"Jonas","family":"Schoenen","sequence":"first","affiliation":[{"name":"Computer Systems Group, Technische Universit\u00e4t Darmstadt, 64283 Darmstadt, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0585-7893","authenticated-orcid":false,"given":"Jonas","family":"Gehrunger","sequence":"additional","affiliation":[{"name":"Computer Systems Group, Technische Universit\u00e4t Darmstadt, 64283 Darmstadt, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-9750-6781","authenticated-orcid":false,"given":"Leon","family":"Mayrhofer","sequence":"additional","affiliation":[{"name":"Computer Systems Group, Technische Universit\u00e4t Darmstadt, 64283 Darmstadt, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1501-2795","authenticated-orcid":false,"given":"Timo","family":"Oster","sequence":"additional","affiliation":[{"name":"Integrated Electronic Systems Lab, Technische Universit\u00e4t Darmstadt, 64283 Darmstadt, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8714-9059","authenticated-orcid":false,"given":"Eszter","family":"Piros","sequence":"additional","affiliation":[{"name":"Advanced Thin Film Technology Division, Technische Universit\u00e4t Darmstadt, 64287 Darmstadt, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Taewook","family":"Kim","sequence":"additional","affiliation":[{"name":"Advanced Thin Film Technology Division, Technische Universit\u00e4t Darmstadt, 64287 Darmstadt, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexey","family":"Arzumanov","sequence":"additional","affiliation":[{"name":"Advanced Thin Film Technology Division, Technische Universit\u00e4t Darmstadt, 64287 Darmstadt, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0470-5318","authenticated-orcid":false,"given":"Enrique","family":"Miranda","sequence":"additional","affiliation":[{"name":"Departament d\u2019Enginyeria Electr\u00f2nica, Universitat Aut\u00f2noma de Barcelona, 08193 Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6675-0221","authenticated-orcid":false,"given":"Klaus","family":"Hofmann","sequence":"additional","affiliation":[{"name":"Integrated Electronic Systems Lab, Technische Universit\u00e4t Darmstadt, 64283 Darmstadt, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8185-4275","authenticated-orcid":false,"given":"Lambert","family":"Alff","sequence":"additional","affiliation":[{"name":"Advanced Thin Film Technology Division, Technische Universit\u00e4t Darmstadt, 64287 Darmstadt, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5516-7826","authenticated-orcid":false,"given":"Christian","family":"Hochberger","sequence":"additional","affiliation":[{"name":"Computer Systems Group, Technische Universit\u00e4t Darmstadt, 64283 Darmstadt, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2026,3,31]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"4","DOI":"10.1109\/MCAS.2021.3071607","article-title":"FPGA Architecture: Principles and Progression","volume":"21","author":"Boutros","year":"2021","journal-title":"IEEE Circuits Syst. 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