{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T11:47:35Z","timestamp":1775044055560,"version":"3.50.1"},"reference-count":34,"publisher":"MDPI AG","issue":"4","license":[{"start":{"date-parts":[[2026,3,31]],"date-time":"2026-03-31T00:00:00Z","timestamp":1774915200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Micromachines"],"abstract":"<jats:p>With the advancement of semiconductor technology, the Network-on-Chip (NoC) has become a critical architecture for communication between multiple cores. However, failures caused by factors such as manufacturing processes can degrade its performance and stability, making efficient topology reconstruction algorithms particularly important. Conventional 2D mesh reconstruction yields irregular topologies, increasing network latency and complicating system scheduling and deployment. While REmesh structures maintain topological regularity, they struggle to balance algorithmic complexity, success rates, and reconstruction costs. This paper proposes a monotonic path shift (MPS) topological reconstruction algorithm for REmesh NoCs with core-level redundancy, based on local rapid recovery. This algorithm localizes reconstruction decisions by establishing monotonic paths between failed cores and redundant cores for recovery. It incorporates region retention and local fallback mechanisms to suppress path conflicts among multiple failed cores. Theoretical analysis shows that MPS provides an upper bound on the runtime of the algorithm, significantly reducing its time complexity. Experimental results indicate that its reconstruction success rate is comparable to that of the ACTR algorithm, with both maintaining a high repair rate even under high fault density. In terms of core reuse rate, MPS achieves significant improvements over BTTR, BSTR, and ACTR, with an average increase of approximately 10% under low-fault conditions, effectively utilizing remaining computational resources. Concurrently, the algorithm substantially reduces average migration time, accelerating recovery by several orders of magnitude in large-scale low-fault scenarios and markedly lowering online recovery overhead.<\/jats:p>","DOI":"10.3390\/mi17040438","type":"journal-article","created":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T10:09:21Z","timestamp":1775038161000},"page":"438","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Topology Reconfiguration for NoCs: A Fast Reconfiguration Algorithm Based on Monotonic Path Shifting"],"prefix":"10.3390","volume":"17","author":[{"given":"Mingzhi","family":"Zhang","sequence":"first","affiliation":[{"name":"College of Computer and Control Engineering, Northeast Forestry University, Harbin 150040, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhijia","family":"Wang","sequence":"additional","affiliation":[{"name":"College of Computer and Control Engineering, Northeast Forestry University, Harbin 150040, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-1123-6812","authenticated-orcid":false,"given":"Zhenxing","family":"Wang","sequence":"additional","affiliation":[{"name":"College of Computer and Control Engineering, Northeast Forestry University, Harbin 150040, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dali","family":"Xu","sequence":"additional","affiliation":[{"name":"College of Computer and Control Engineering, Northeast Forestry University, Harbin 150040, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Na","family":"Niu","sequence":"additional","affiliation":[{"name":"College of Computer and Control Engineering, Northeast Forestry University, Harbin 150040, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2026,3,31]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"82","DOI":"10.1109\/JPROC.1998.658762","article-title":"Cramming More Components onto Integrated Circuits","volume":"86","author":"Moore","year":"1998","journal-title":"Proc. IEEE"},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"256","DOI":"10.1109\/JSSC.1974.1050511","article-title":"Design of Ion-Implanted MOSFET\u2019s with Very Small Physical Dimensions","volume":"9","author":"Dennard","year":"1974","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"48","DOI":"10.1145\/3282307","article-title":"A New Golden Age for Computer Architecture","volume":"62","author":"Hennessy","year":"2019","journal-title":"Commun. ACM"},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"122","DOI":"10.1109\/MM.2012.17","article-title":"Dark Silicon and the End of Multicore Scaling","volume":"32","author":"Esmaeilzadeh","year":"2012","journal-title":"IEEE Micro"},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"490","DOI":"10.1109\/5.920580","article-title":"The Future of Wires","volume":"89","author":"Ho","year":"2001","journal-title":"Proc. IEEE"},{"key":"ref_6","doi-asserted-by":"crossref","unstructured":"Dally, W.J., and Towles, B. (2001). Route Packets, Not Wires: On-Chip Interconnection Networks. Proceedings of the 38th Design Automation Conference (DAC), Las Vegas, NV, USA, 18\u201322 June 2001, ACM.","DOI":"10.1145\/378239.379048"},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/2.976921","article-title":"Networks on Chips: A New SoC Paradigm","volume":"35","author":"Benini","year":"2002","journal-title":"Computer"},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1132952.1132953","article-title":"A Survey of Research and Practices of Network-on-Chip","volume":"38","author":"Bjerregaard","year":"2006","journal-title":"ACM Comput. Surv."},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"14","DOI":"10.1109\/MM.2003.1225959","article-title":"Trends and Challenges in VLSI Circuit Reliability","volume":"23","author":"Constantinescu","year":"2003","journal-title":"IEEE Micro"},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1109\/TDSC.2004.2","article-title":"Basic Concepts and Taxonomy of Dependable and Secure Computing","volume":"1","author":"Avizienis","year":"2004","journal-title":"IEEE Trans. Dependable Secur. Comput."},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"59","DOI":"10.1145\/2886781","article-title":"A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip","volume":"48","author":"Werner","year":"2016","journal-title":"ACM Comput. Surv."},{"key":"ref_12","doi-asserted-by":"crossref","unstructured":"Feng, A., Lu, Y., Jantsch, A., Zhang, M., and Xing, Z. (2010). A Reconfigurable Fault-Tolerant Deflection Routing Algorithm Based on Reinforcement Learning for Network-on-Chip. Proceedings of the IEEE\/ACM International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS), Scottsdale, AZ, USA, 24\u201329 October 2010, ACM.","DOI":"10.1145\/1921249.1921254"},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"1173","DOI":"10.1109\/TVLSI.2008.2002108","article-title":"On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems","volume":"17","author":"Zhang","year":"2009","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_14","doi-asserted-by":"crossref","unstructured":"Zhang, L., Han, Y., Xu, Q., and Li, X. (2008). Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE), Munich, Germany, 10\u201314 March 2008, ACM.","DOI":"10.1109\/DATE.2008.4484787"},{"key":"ref_15","doi-asserted-by":"crossref","unstructured":"Hosseinabady, M., and N\u00fa\u00f1ez-Y\u00e1\u00f1ez, J.L. (2008). Fault-Tolerant Dynamically Reconfigurable NoC-Based SoC. Proceedings of the 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Leuven, Belgium, 2\u20134 July 2008, ACM.","DOI":"10.1109\/ASAP.2008.4580150"},{"key":"ref_16","doi-asserted-by":"crossref","unstructured":"Beldachi, A.F., and N\u00fa\u00f1ez-Y\u00e1\u00f1ez, J.L. (2012). Reconfigure Router Design and Evaluation for the FPGA-Friendly SoCWire Network-on-Chip. Proceedings of the Annual FPGA Conference (FPGAworld \u201912), Oslo, Norway, 4 September 2012, ACM. Art. 1, 6 pages.","DOI":"10.1145\/2451636.2451637"},{"key":"ref_17","doi-asserted-by":"crossref","unstructured":"Hogan, J.A., Weber, R.J., LaMeres, B.J., and Kaiser, T. (2013). Network-on-Chip for a Partially Reconfigurable FPGA System. Proceedings of the 27th International ACM Conference on International Conference on Supercomputing (ICS), Eugene, OR, USA, 10\u201314 June 2013, ACM.","DOI":"10.1145\/2464996.2467285"},{"key":"ref_18","doi-asserted-by":"crossref","unstructured":"Heiner, J., Sellers, B., Wirthlin, M., and Kalb, J. (2009). FPGA Partial Reconfiguration via Configuration Scrubbing. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Prague, Czech Republic, 31 August\u20132 September 2009, IEEE.","DOI":"10.1109\/FPL.2009.5272543"},{"key":"ref_19","doi-asserted-by":"crossref","unstructured":"Cannon, M., Keller, A., and Wirthlin, M. (2018). Improving the Effectiveness of TMR Designs on FPGAs with SEU-Aware Incremental Placement. Proceedings of the IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boulder, CO, USA, 29 April\u20131 May 2018, IEEE.","DOI":"10.1109\/FCCM.2018.00031"},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"86","DOI":"10.1016\/j.micpro.2018.04.006","article-title":"Reconfiguration Control Networks for FPGA-Based TMR Systems with Modular Error Recovery","volume":"60","author":"Nguyen","year":"2018","journal-title":"Microprocess. Microsyst."},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"39","DOI":"10.1016\/j.sysarc.2018.10.001","article-title":"A Survey on Fault-Tolerant Application Mapping Techniques for Network-on-Chip","volume":"92","author":"Kadri","year":"2019","journal-title":"J. Syst. Archit."},{"key":"ref_22","doi-asserted-by":"crossref","first-page":"1950111","DOI":"10.1142\/S0218126619501111","article-title":"Algorithms for Reconfiguring NoC-Based Fault-Tolerant Multiprocessor Arrays","volume":"28","author":"Wu","year":"2019","journal-title":"J. Circuits Syst. Comput."},{"key":"ref_23","doi-asserted-by":"crossref","unstructured":"Fu, F.-F., Niu, N., Xian, X.-H., Wang, J.-X., and Lai, F.-C. (2017). An Optimized Topology Reconfiguration Bidirectional Searching Fault-Tolerant Algorithm for REmesh Network-on-Chip. Proceedings of the IEEE 12th International Conference on ASIC (ASICON), Guiyang, China, 25\u201328 October 2017, IEEE.","DOI":"10.1109\/ASICON.2017.8252473"},{"key":"ref_24","doi-asserted-by":"crossref","unstructured":"Niu, N., Fu, F.-F., Li, H., Lai, F.-C., and Wang, J.-X. (2017). A Novel Topology Reconfiguration Backtracking Algorithm for 2D REmesh Networks-on-Chip. Parallel Architecture, Algorithm and Programming, Springer.","DOI":"10.1007\/978-981-10-6442-5_5"},{"key":"ref_25","doi-asserted-by":"crossref","unstructured":"Hou, B., Xu, D., Fu, F., Yang, B., and Niu, N. (2025). An Optimized Core Distribution Adaptive Topology Reconfiguration Algorithm for NoC-Based Embedded Systems. Micromachines, 16.","DOI":"10.3390\/mi16040421"},{"key":"ref_26","first-page":"140","article-title":"Memory Built-In Self-Repair and Correction for Improving Yield: A Review","volume":"14","author":"Sontakke","year":"2024","journal-title":"Int. J. Electr. Comput. Eng."},{"key":"ref_27","unstructured":"Shivakumar, P., Keckler, S.W., Moore, C.R., and Burger, D. (2003). Exploiting Microarchitectural Redundancy for Defect Tolerance. Proceedings of the 21st International Conference on Computer Design (ICCD), San Jose, CA, USA, 13 October 2003, IEEE."},{"key":"ref_28","doi-asserted-by":"crossref","first-page":"104904","DOI":"10.1016\/j.jpdc.2024.104904","article-title":"Efficient Topology Reconfiguration for NoC-Based Multiprocessors: A Greedy-Memetic Algorithm","volume":"190","author":"Qian","year":"2024","journal-title":"J. Parallel Distrib. Comput."},{"key":"ref_29","doi-asserted-by":"crossref","first-page":"621","DOI":"10.1007\/s11235-017-0412-2","article-title":"Hardware Implementation of Fault Tolerance NoC Core Mapping","volume":"68","author":"Beechu","year":"2018","journal-title":"Telecommun. Syst."},{"key":"ref_30","doi-asserted-by":"crossref","first-page":"107441","DOI":"10.1016\/j.compeleceng.2021.107441","article-title":"An Adaptive Core Mapping Algorithm on NoC for Future Heterogeneous System-on-Chip","volume":"95","author":"Kumar","year":"2021","journal-title":"Comput. Electr. Eng."},{"key":"ref_31","doi-asserted-by":"crossref","first-page":"45935","DOI":"10.1109\/ACCESS.2021.3066537","article-title":"Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA","volume":"9","author":"Bhanu","year":"2021","journal-title":"IEEE Access"},{"key":"ref_32","doi-asserted-by":"crossref","first-page":"76759","DOI":"10.1109\/ACCESS.2021.3082852","article-title":"Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA","volume":"9","author":"Bhanu","year":"2021","journal-title":"IEEE Access"},{"key":"ref_33","doi-asserted-by":"crossref","unstructured":"Wu, Z.X., Wang, J.X., Zhang, J.Y., Wang, X.Y., and Fu, F.F. (2012). Exploration of a Reconfigurable 2D Mesh Network-on-Chip Architecture and a Topology Reconfiguration Algorithm. Proceedings of the IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Xi\u2019an, China, 29 October\u20131 November 2012, IEEE. Article 6466732.","DOI":"10.1109\/ICSICT.2012.6466732"},{"key":"ref_34","doi-asserted-by":"crossref","first-page":"547","DOI":"10.1109\/TC.1987.1676939","article-title":"Deadlock-Free Message Routing in Multiprocessor Interconnection Networks","volume":"36","author":"Dally","year":"1987","journal-title":"IEEE Trans. Comput."}],"container-title":["Micromachines"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2072-666X\/17\/4\/438\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T10:20:48Z","timestamp":1775038848000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2072-666X\/17\/4\/438"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,3,31]]},"references-count":34,"journal-issue":{"issue":"4","published-online":{"date-parts":[[2026,4]]}},"alternative-id":["mi17040438"],"URL":"https:\/\/doi.org\/10.3390\/mi17040438","relation":{},"ISSN":["2072-666X"],"issn-type":[{"value":"2072-666X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,3,31]]}}}