{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,9]],"date-time":"2026-04-09T08:59:55Z","timestamp":1775725195229,"version":"3.50.1"},"reference-count":24,"publisher":"MDPI AG","issue":"4","license":[{"start":{"date-parts":[[2026,4,9]],"date-time":"2026-04-09T00:00:00Z","timestamp":1775692800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Micromachines"],"abstract":"<jats:p>To meet the demands for miniaturization, lightweight design, and high performance in modern electronic systems, advanced 3D TSV technology enables a substantial increase in storage capacity even within physically constrained form factors. This paper proposes a schematic design methodology and system-level integrated modeling approach for a four-layer stacked micro-module based on wafer-level packaging. By leveraging heterogeneous chip fan-out technology and TSV-based vertical stacking, the fabricated DDR3 micro-module achieves a compact footprint of 14 \u00d7 9 \u00d7 3.5 mm, a storage capacity of 4 GB, and a 64-bit bus width. Compared to conventional board-level mounting, the module reduces the footprint area by 95%. Following comprehensive multi-level testing, the micro-module fully complies with standard protocol requirements, enabling a paradigm shift in form factors for mobile computing devices while enhancing computational density and energy efficiency in data center server applications.<\/jats:p>","DOI":"10.3390\/mi17040459","type":"journal-article","created":{"date-parts":[[2026,4,9]],"date-time":"2026-04-09T07:48:07Z","timestamp":1775720887000},"page":"459","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Design and Implementation of High-Capacity DDR3 Micro-Module Based on 3D TSV Advanced Packaging"],"prefix":"10.3390","volume":"17","author":[{"given":"Haoyue","family":"Ji","sequence":"first","affiliation":[{"name":"School of Electro-Mechnical Engineering, Xidian University, Xi\u2019an 710071, China"},{"name":"The 58th Research Institute of China Electronics Technology Group Corporation, Wuxi 214062, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liang","family":"Zeng","sequence":"additional","affiliation":[{"name":"The 58th Research Institute of China Electronics Technology Group Corporation, Wuxi 214062, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hongwen","family":"Qian","sequence":"additional","affiliation":[{"name":"The 58th Research Institute of China Electronics Technology Group Corporation, Wuxi 214062, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenchao","family":"Tian","sequence":"additional","affiliation":[{"name":"School of Electro-Mechnical Engineering, Xidian University, Xi\u2019an 710071, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jingjing","family":"Lin","sequence":"additional","affiliation":[{"name":"The 58th Research Institute of China Electronics Technology Group Corporation, Wuxi 214062, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuhe","family":"Duan","sequence":"additional","affiliation":[{"name":"The 58th Research Institute of China Electronics Technology Group Corporation, Wuxi 214062, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2026,4,9]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"125357","DOI":"10.1016\/j.applthermaleng.2025.125738","article-title":"A Multilevel-Multiphysics Modeling and Simulation Approach for Multichip Electronics","volume":"266","author":"Zhou","year":"2025","journal-title":"Appl. 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