{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,31]],"date-time":"2026-08-31T03:13:31Z","timestamp":1788146011181,"version":"build-2803163510"},"reference-count":104,"publisher":"MDPI AG","issue":"9","license":[{"start":{"date-parts":[[2026,8,30]],"date-time":"2026-08-30T00:00:00Z","timestamp":1788048000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Micromachines"],"abstract":"<jats:p>As transistor scaling approaches physical and economic limits, advanced packaging has become an important approach to continued system scaling. This review compares two-dimensional (2D), two- and-a-half-dimensional (2.5D), and three-dimensional (3D) integration technologies, including silicon interposers, localized silicon bridges, redistribution layer (RDL) fan-out platforms, and vertical die stacking. The comparison focuses on interconnect geometry, bandwidth, energy efficiency, thermal and mechanical constraints, manufacturing maturity, cost, and major failure mechanisms. Representative applications in power electronics, high-performance computing (HPC), artificial intelligence (AI), radio frequency (RF) systems, and micro-electromechanical systems (MEMS) are discussed together with their packaging requirements. The relationships between package structure and thermal, mechanical, and electrical reliability are also examined. Emerging technologies, including vertical power delivery, glass substrates, hybrid bonding, and AI-assisted multiphysics design, are further discussed in terms of their role in future heterogeneous integration. Finally, a near-, medium-, and long-term roadmap is presented to summarize the main scaling targets and qualification requirements for larger, denser, and higher-power integrated systems.<\/jats:p>","DOI":"10.3390\/mi17091039","type":"journal-article","created":{"date-parts":[[2026,8,31]],"date-time":"2026-08-31T02:08:58Z","timestamp":1788142138000},"page":"1039","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Advanced Electronic Packaging Technologies: A Comparative Review of Architectures, Applications, Reliability"],"prefix":"10.3390","volume":"17","author":[{"given":"Yuxian","family":"Huang","sequence":"first","affiliation":[{"name":"College of Electronics and Information Engineering, Shenzhen University, Shenzhen 518060, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7396-0959","authenticated-orcid":false,"given":"Dingguan","family":"Wang","sequence":"additional","affiliation":[{"name":"College of Electronics and Information Engineering, Shenzhen University, Shenzhen 518060, China"},{"name":"State Key Laboratory of Radio Frequency Heterogeneous Integration, Shenzhen University, Shenzhen 518060, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Qianyi","family":"Li","sequence":"additional","affiliation":[{"name":"College of Physics and Optoelectronic Engineering, Shenzhen University, Shenzhen 518060, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhiming","family":"Pan","sequence":"additional","affiliation":[{"name":"College of Electronics and Information Engineering, Shenzhen University, Shenzhen 518060, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"1968","published-online":{"date-parts":[[2026,8,30]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"81","DOI":"10.1109\/MDAT.2023.3302809","article-title":"Furthering Moore\u2019s Law Integration Benefits in the Chiplet Era","volume":"41","author":"Munoz","year":"2024","journal-title":"IEEE Des. Test"},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"1425","DOI":"10.1109\/TCPMT.2020.3021317","article-title":"Foreword: Special Section on \u201cThe Reliability of Advanced Microelectronic Packaging\u2014Part I: Management of Thermal Effects\u201d","volume":"10","author":"Li","year":"2020","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"351","DOI":"10.1109\/OJSSCS.2024.3506694","article-title":"High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI\/ML Applications: Challenges and Solutions","volume":"4","author":"Li","year":"2024","journal-title":"IEEE Open J. Solid-State Circuits Soc."},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1109\/TCPMT.2017.2787938","article-title":"Foreword: Special Section on Recent Progress in the Electrical Design of Advanced Package and Systems","volume":"8","author":"Han","year":"2018","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"1203","DOI":"10.1109\/TCPMT.2025.3566026","article-title":"Numerical Analysis and Optimization of Chip-Level Drop Impact Reliability for Chiplet Based on Si Interposer","volume":"15","author":"Yin","year":"2025","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_6","doi-asserted-by":"crossref","unstructured":"Agarwal, R., Cheng, P., Shah, P., Wilkerson, B., Swaminathan, R., Wuu, J., and Mandalapu, C. (June, January 31). 3D Packaging for Heterogeneous Integration. Proceedings of the 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), San Diego, CA, USA.","DOI":"10.1109\/ECTC51906.2022.00178"},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Wang, H., Ma, J., Yang, Y., Gong, M., and Wang, Q. (2023). A Review of System-in-Package Technologies: Application and Reliability of Advanced Packaging. Micromachines, 14.","DOI":"10.3390\/mi14061149"},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"1455","DOI":"10.1016\/j.fmre.2023.04.014","article-title":"Challenges and Prospects for Advanced Packaging","volume":"4","author":"Chen","year":"2024","journal-title":"Fundam. Res."},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"Lau, J.H. (2014). Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration. J. Electron. Packag., 136.","DOI":"10.1115\/1.4028629"},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"1544","DOI":"10.1109\/TCPMT.2018.2848649","article-title":"Fan-Out Wafer-Level Packaging for Heterogeneous Integration","volume":"8","author":"Lau","year":"2018","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_11","doi-asserted-by":"crossref","unstructured":"Lau, J.H. (2019). Heterogeneous Integrations, Springer.","DOI":"10.1007\/978-981-13-7224-7"},{"key":"ref_12","doi-asserted-by":"crossref","first-page":"1301","DOI":"10.1109\/TCPMT.2021.3096786","article-title":"Hybrid Substrate by Fan-Out RDL-First Panel-Level Packaging","volume":"11","author":"Lau","year":"2021","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"1271","DOI":"10.1109\/TCPMT.2022.3194374","article-title":"Recent Advances and Trends in Multiple System and Heterogeneous Integration with TSV-Less Interposers","volume":"12","author":"Lau","year":"2022","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"228","DOI":"10.1109\/TCPMT.2022.3144461","article-title":"Recent Advances and Trends in Advanced Packaging","volume":"12","author":"Lau","year":"2022","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_15","doi-asserted-by":"crossref","unstructured":"Lau, J.H. (2023). Chiplet Design and Heterogeneous Integration Packaging, Springer.","DOI":"10.1007\/978-981-19-9917-8"},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"4071","DOI":"10.1109\/TED.2017.2737644","article-title":"Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology","volume":"64","author":"Hou","year":"2017","journal-title":"IEEE Trans. Electron Devices"},{"key":"ref_17","doi-asserted-by":"crossref","first-page":"1789","DOI":"10.1016\/j.jmrt.2025.03.212","article-title":"Effects of Electrodeposition Current Density and Additives on the Microstructure and Mechanical Properties of Copper Films","volume":"36","author":"Wu","year":"2025","journal-title":"J. Mater. Res. Technol."},{"key":"ref_18","doi-asserted-by":"crossref","unstructured":"Duan, G., Kanaoka, Y., McRee, R., Nie, B., and Manepalli, R. (July, January 1). Die Embedding Challenges for EMIB Advanced Packaging Technology. Proceedings of the 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, CA, USA.","DOI":"10.1109\/ECTC32696.2021.00012"},{"key":"ref_19","doi-asserted-by":"crossref","unstructured":"Duan, G., Kanaoka, Y., McRee, R., Li, Y., Liu, M.L., Yeon, H.S., Jones, J., Tanaka, H., May, A., and Ranjan, R. (2022, January 3\u20137). Advanced Substrate Packaging Technologies for Enabling Heterogeneous Integration (HI) Applications. Proceedings of the 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA.","DOI":"10.1109\/IEDM45625.2022.10019355"},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"1952","DOI":"10.1109\/TCPMT.2019.2942708","article-title":"Embedded Multidie Interconnect Bridge\u2014A Localized, High-Density Multichip Packaging Interconnect","volume":"9","author":"Mahajan","year":"2019","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_21","unstructured":"(2026, August 04). TSMC CoWoS Technology: CoWoS-L with RDL Interposer and Local Silicon Interconnect. Available online: https:\/\/3dfabric.tsmc.com\/english\/dedicatedFoundry\/technology\/cowos.htm."},{"key":"ref_22","unstructured":"IBM Research (2026, August 04). Scalable Advanced DBHi Chiplet Package Using Silicon Bridge with 30 \u03bcm-Pitch Solder Joints. ECTC 2024. Available online: https:\/\/research.ibm.com\/publications\/scalable-advanced-dbhi-chiplet-package-using-silicon-bridge-with-30-m-pitch-solder-joints."},{"key":"ref_23","unstructured":"IBM Research (2026, August 04). Direct Bonded Heterogeneous Integration (DBHi): Surface Bridge Approach for Die Tiling. ECTC 2023. Available online: https:\/\/research.ibm.com\/publications\/direct-bonded-heterogeneous-integration-dbhi-surface-bridge-approach-for-die-tiling."},{"key":"ref_24","unstructured":"Intel (2026, August 04). Quality and Reliability, Volume 6: Intel Advanced Packaging Technology. Available online: https:\/\/cdrdv2-public.intel.com\/826148\/Volume%206%20Intel%20Advanced%20Packaging%20Technology.pdf."},{"key":"ref_25","unstructured":"Intel Foundry (2026, August 04). Intel 18A Platform Technology and 3D Integration. Available online: https:\/\/www.intel.com\/content\/www\/us\/en\/foundry\/process\/18a.html."},{"key":"ref_26","doi-asserted-by":"crossref","first-page":"71","DOI":"10.1109\/MSP.2019.2909074","article-title":"Radar-on-Chip\/in-Package in Autonomous Driving Vehicles and Intelligent Transport Systems: Opportunities and Challenges","volume":"36","author":"Saponara","year":"2019","journal-title":"IEEE Signal Process. Mag."},{"key":"ref_27","doi-asserted-by":"crossref","unstructured":"Hwang, H.Y., Lee, J.S., Seok, T.J., Forencich, A., Grant, H.R., Knutson, D., Quack, N., Han, S., Muller, R.S., and Papen, G.C. (2017). Flip Chip Packaging of Digital Silicon Photonics MEMS Switch for Cloud Computing and Data Centre. IEEE Photonics J., 9.","DOI":"10.1109\/JPHOT.2017.2704097"},{"key":"ref_28","doi-asserted-by":"crossref","unstructured":"Zhao, X., Cheng, M., Sheng, N., Zhao, Z., Li, W., Qiao, W., and Jia, Y. (2024, January 7\u20139). Multi-Scale and Multi-Process Simulation of Integrated Fan-Out Packaging for Reliability Improvement. Proceedings of the 2024 25th International Conference on Electronic Packaging Technology (ICEPT), Tianjin, China.","DOI":"10.1109\/ICEPT63120.2024.10668577"},{"key":"ref_29","first-page":"26","article-title":"Enabling the 5G RF Front-End Module Evolution with the DSMBGA Package","volume":"25","author":"Zwenger","year":"2021","journal-title":"Chip Scale Rev."},{"key":"ref_30","doi-asserted-by":"crossref","unstructured":"Li, X., Pan, Z., Hao, W., Miao, R., Yue, Z., and Wang, A. (2025). Interposer-Based ESD Protection: A Potential Solution for \u03bc-Packaging Reliability of 3D Chips. Micromachines, 16.","DOI":"10.3390\/mi16040488"},{"key":"ref_31","doi-asserted-by":"crossref","unstructured":"Li, Z., Luo, H., Jiang, Y., Liu, H., Xu, L., Cao, K., Wu, H., Gao, P., and Liu, H. (2024). Comprehensive Review and Future Prospects on Chip-Scale Thermal Management: Core of Data Center\u2019s Thermal Management. Appl. Therm. Eng., 251.","DOI":"10.1016\/j.applthermaleng.2024.123612"},{"key":"ref_32","doi-asserted-by":"crossref","first-page":"894","DOI":"10.1109\/TCPMT.2025.3531429","article-title":"Research on Silicon-Based Multilayer 2.5-D Integration for MOS Switch Modules","volume":"15","author":"Zhang","year":"2025","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_33","doi-asserted-by":"crossref","first-page":"239","DOI":"10.1109\/JESTPE.2019.2951801","article-title":"A Review of SiC Power Module Packaging Technologies: Challenges, Advances, and Emerging Issues","volume":"8","author":"Lee","year":"2020","journal-title":"IEEE J. Emerg. Sel. Top. Power Electron."},{"key":"ref_34","doi-asserted-by":"crossref","first-page":"1480","DOI":"10.1109\/TCPMT.2021.3105003","article-title":"Thermal Design, Optimization, and Packaging of Planar Magnetic Components","volume":"11","author":"Dede","year":"2021","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_35","doi-asserted-by":"crossref","first-page":"223","DOI":"10.1109\/JESTPE.2019.2947645","article-title":"Review of Packaging Schemes for Power Module","volume":"8","author":"Hou","year":"2020","journal-title":"IEEE J. Emerg. Sel. Top. Power Electron."},{"key":"ref_36","doi-asserted-by":"crossref","first-page":"854","DOI":"10.1109\/TCPMT.2018.2860998","article-title":"Thermal Optimization and Characterization of SiC-Based High Power Electronics Packages With Advanced Thermal Design","volume":"9","author":"Tang","year":"2019","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_37","doi-asserted-by":"crossref","first-page":"8980","DOI":"10.1109\/TIE.2017.2723873","article-title":"An SiC-Based Half-Bridge Module With an Improved Hybrid Packaging Method for High Power Density Applications","volume":"64","author":"Chen","year":"2017","journal-title":"IEEE Trans. Ind. Electron."},{"key":"ref_38","doi-asserted-by":"crossref","first-page":"157","DOI":"10.1109\/TCPMT.2024.3467274","article-title":"Thermal Characteristics Analysis and Optimization of Heterogeneous 2.5-D Package Under System-Level Conditions","volume":"15","author":"Shih","year":"2025","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_39","doi-asserted-by":"crossref","first-page":"131","DOI":"10.1109\/TCPMT.2024.3480090","article-title":"Characterization of Emerging Polymer Dielectric Materials for Advanced Packaging Applications","volume":"15","author":"Dwarakanath","year":"2025","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_40","doi-asserted-by":"crossref","first-page":"1177","DOI":"10.1109\/TCPMT.2021.3091555","article-title":"Diamond-Incorporated Flip-Chip Integration for Thermal Management of GaN and Ultra-Wide Bandgap RF Power Amplifiers","volume":"11","author":"Shoemaker","year":"2021","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_41","doi-asserted-by":"crossref","first-page":"215","DOI":"10.1109\/TED.2022.3223632","article-title":"Board-Level Drop Impact Reliability Analysis of Dual-Side Molding System-in-Package (SiP) Modules","volume":"70","author":"Shih","year":"2023","journal-title":"IEEE Trans. Electron Devices"},{"key":"ref_42","doi-asserted-by":"crossref","first-page":"44","DOI":"10.1109\/TCPMT.2019.2955822","article-title":"Chip-Package-Board Reliability of System-in-Package Using Laminate Chip Embedding Technology Based on Cu Leadframe","volume":"10","author":"Fruehauf","year":"2020","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_43","doi-asserted-by":"crossref","first-page":"4116","DOI":"10.1109\/TR.2025.3558449","article-title":"A Review of Prognostics Methods for Electronic Packages: From a Structure-Aware System-Level Perspective","volume":"74","author":"Zhang","year":"2025","journal-title":"IEEE Trans. Rel."},{"key":"ref_44","doi-asserted-by":"crossref","unstructured":"Hariharan, G., Yip, L., Chaware, R., Singh, I., Shen, M., Ng, K., and Xu, A. (June, January 30). Reliability Evaluations on 3D IC Package beyond JEDEC. Proceedings of the 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA.","DOI":"10.1109\/ECTC.2017.298"},{"key":"ref_45","doi-asserted-by":"crossref","first-page":"3371","DOI":"10.1109\/TR.2025.3556255","article-title":"Reliability Study of Critical Structural Redistribution Layers in Advanced Packaging: A Review","volume":"74","author":"Jin","year":"2025","journal-title":"IEEE Trans. Reliab."},{"key":"ref_46","doi-asserted-by":"crossref","first-page":"1624","DOI":"10.1109\/TCPMT.2023.3317383","article-title":"Thermomechanical Challenges of 2.5-D Packaging: A Review of Warpage and Interconnect Reliability","volume":"13","author":"Kim","year":"2023","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_47","doi-asserted-by":"crossref","first-page":"75285","DOI":"10.1109\/ACCESS.2023.3297222","article-title":"Thermal Performance Analysis of Carbon Materials Based TSV in Three Dimensional Integrated Circuits","volume":"11","author":"Xu","year":"2023","journal-title":"IEEE Access"},{"key":"ref_48","doi-asserted-by":"crossref","first-page":"1753","DOI":"10.1109\/TED.2021.3062314","article-title":"Active Thermal Management of High-Power LED Through Chip on Thermoelectric Cooler","volume":"68","author":"Li","year":"2021","journal-title":"IEEE Trans. Electron Devices"},{"key":"ref_49","doi-asserted-by":"crossref","unstructured":"He, W., Yin, E., Zhou, F., Zhao, Y., Hu, D., Li, J., and Li, Q. (2024). Integrated Manifold Microchannels and Near-Junction Cooling for Enhanced Thermal Management in 3D Heterogeneous Packaging Technology. Energy, 305.","DOI":"10.1016\/j.energy.2024.132263"},{"key":"ref_50","doi-asserted-by":"crossref","first-page":"251","DOI":"10.1109\/TCPMT.2024.3357126","article-title":"Reducing Thermal Interface Resistance by Oxygen Plasma Treatment for FCBGA Advanced Package","volume":"14","author":"Yi","year":"2024","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_51","doi-asserted-by":"crossref","first-page":"448","DOI":"10.1109\/LED.2024.3351990","article-title":"Heterogeneous Integration of Diamond-on-Chip-on-Glass Interposer for Efficient Thermal Management","volume":"45","author":"Zhong","year":"2024","journal-title":"IEEE Electron Device Lett."},{"key":"ref_52","doi-asserted-by":"crossref","unstructured":"Tang, S., Chen, J., Hu, Y.B., Yu, C., Lu, H., Zhang, S., and Xiong, K. (2024). Brief Overview of the Impact of Thermal Stress on the Reliability of through Silicon via: Analysis, Characterization, and Enhancement. Mater. Sci. Semicond. Process., 183.","DOI":"10.1016\/j.mssp.2024.108745"},{"key":"ref_53","doi-asserted-by":"crossref","unstructured":"Xu, S., Zhang, Y., Li, Q., and Chen, X. (2025). Multi-Physical Field Coupling Effect in Micro Pin-Fin Channel Cooling with Coaxial-like through-Silicon via (TSV) for Three-Dimensional Integrated Chip (3D-IC). Appl. Therm. Eng., 258.","DOI":"10.1016\/j.applthermaleng.2024.124815"},{"key":"ref_54","doi-asserted-by":"crossref","first-page":"1792","DOI":"10.1109\/TCPMT.2024.3452637","article-title":"Electrical\u2013Thermal Co-Analysis of Through-Silicon Vias (TSVs) Integrated Within Micropin-Fin Heatsink for 3-D Heterogeneous Integration (HI)","volume":"14","author":"Chung","year":"2024","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_55","doi-asserted-by":"crossref","first-page":"2161","DOI":"10.1109\/TPDS.2024.3459414","article-title":"An Evaluation Framework for Dynamic Thermal Management Strategies in 3D MultiProcessor System-on-Chip Co-Design","volume":"35","author":"Huang","year":"2024","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"ref_56","doi-asserted-by":"crossref","unstructured":"Yokota, S., Hasegawa, R., Monta, K., Okidono, T., Miki, T., and Nagata, M. (2024, January 25). Thermal Flow Simuation and Measurements of 3D Si Chip Stacks with TSVs. Proceedings of the 2024 International 3D Systems Integration Conference (3DIC), Sendai, Japan.","DOI":"10.1109\/3DIC63395.2024.10830034"},{"key":"ref_57","doi-asserted-by":"crossref","first-page":"104","DOI":"10.1109\/TCPMT.2024.3516653","article-title":"Toward TSV-Compatible Microfluidic Cooling for 3D ICs","volume":"15","author":"Yan","year":"2025","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_58","doi-asserted-by":"crossref","unstructured":"Huang, J., Xue, S., Liu, S., Li, G., and Wang, C. (2024, January 7\u20139). 2.5D Chip-Package Warpage Analysis Using RVE-Based Homogenization Method. Proceedings of the 2024 25th International Conference on Electronic Packaging Technology (ICEPT), Tianjin, China.","DOI":"10.1109\/ICEPT63120.2024.10668709"},{"key":"ref_59","doi-asserted-by":"crossref","unstructured":"Liu, T., Liu, S., Hu, X., Dong, F., Chen, Z., Peng, H., and Liu, S. (2024, January 7\u20139). Study on the Effect of Film Process on Interface and Interconnection Reliability in the TSV Structure. Proceedings of the 2024 25th International Conference on Electronic Packaging Technology (ICEPT), Tianjin, China.","DOI":"10.1109\/ICEPT63120.2024.10668688"},{"key":"ref_60","doi-asserted-by":"crossref","unstructured":"Duan, Y., Liu, G., Wang, W., Deng, Q., Li, J., Cao, R., and Wang, C. (2023). Finite Element Modeling and Analysis Method for Predicting and Optimizing the Warpage of Construction before Flip Chip Bonding in System-on-Wafer Process Flow. Microelectron. Reliab., 151.","DOI":"10.1016\/j.microrel.2023.115260"},{"key":"ref_61","doi-asserted-by":"crossref","first-page":"3374","DOI":"10.1016\/j.jmrt.2024.07.043","article-title":"Effect of Joule Heating on the Reliability of Microbumps in 3D IC","volume":"31","author":"Yao","year":"2024","journal-title":"J. Mater. Res. Technol."},{"key":"ref_62","doi-asserted-by":"crossref","first-page":"524","DOI":"10.1109\/TDMR.2020.3004836","article-title":"Effect of Different PBO-Based RDL Structures on Chip-Package Interaction Reliability of Wafer Level Package","volume":"20","author":"Qin","year":"2020","journal-title":"IEEE Trans. Device Mater. Relib."},{"key":"ref_63","doi-asserted-by":"crossref","first-page":"2088","DOI":"10.1109\/TCPMT.2024.3488009","article-title":"Effect of Effective Curing Shrinkage of EMC on Strip Warpage During IC Encapsulation Process","volume":"14","author":"Hu","year":"2024","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_64","doi-asserted-by":"crossref","first-page":"1734","DOI":"10.1109\/TCPMT.2023.3325222","article-title":"Reliability Concerns of TSV-Based 3-D Integration: Impact of Interfacial Crack","volume":"13","author":"Kumari","year":"2023","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_65","doi-asserted-by":"crossref","first-page":"506","DOI":"10.1109\/TCPMT.2024.3487639","article-title":"Failure Analysis on Abnormal Cracking of Flip-Chip Au Bumps During the High Temperature and Humidity Testing","volume":"15","author":"Zhong","year":"2025","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_66","doi-asserted-by":"crossref","first-page":"51","DOI":"10.1109\/TCPMT.2021.3127157","article-title":"Research on Flip-Chip Bonding Process and Thermal Cycle Reliability Simulation of 3-D Stacked Structure","volume":"12","author":"Chen","year":"2022","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_67","doi-asserted-by":"crossref","first-page":"96","DOI":"10.1109\/JEDS.2024.3358830","article-title":"Investigation of Photosensitive Polyimide With Low Coefficient of Thermal Expansion and Excellent Adhesion Strength for Advanced Packaging Applications","volume":"12","author":"Huang","year":"2024","journal-title":"IEEE J. Electron Devices Soc."},{"key":"ref_68","doi-asserted-by":"crossref","unstructured":"Ding, S., Zhao, J., Wu, X., Chen, C., Fang, Z., and Wang, Q. (2025). Curing Kinetics of a Novel Commercial Epoxy-Phenolic Composite Build-up Film for Flip-Chip Ball Grid Array (FCBGA) Substrates. Microelectron. J., 161.","DOI":"10.1016\/j.mejo.2025.106717"},{"key":"ref_69","doi-asserted-by":"crossref","first-page":"682","DOI":"10.1109\/TCPMT.2025.3532769","article-title":"Low-Temperature Solid-State Bonding of Microbumps Arrays With Flat-to-Convex Structure via Plasma-Induced Silver Oxide Nanoparticles","volume":"15","author":"Wang","year":"2025","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_70","doi-asserted-by":"crossref","first-page":"419","DOI":"10.1109\/TCPMT.2019.2893232","article-title":"Hardness Characteristics of Au Cone-Shaped Bumps Targeted for 3-D Packaging Applications","volume":"9","author":"Lim","year":"2019","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_71","doi-asserted-by":"crossref","first-page":"297","DOI":"10.1109\/TCPMT.2022.3145377","article-title":"Thermal and Mechanical Characterization of 2.5-D and Fan-Out Chip on Substrate Chip-First and Chip-Last Packages","volume":"12","author":"Shih","year":"2022","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_72","doi-asserted-by":"crossref","first-page":"4604","DOI":"10.1109\/TR.2025.3580345","article-title":"Application of Embedded Stress Sensors for Third-Generation Reliability of Electronic Systems: Validation and Calibration of Mechanical Models in Fan-Out Wafer-Level Packaging","volume":"74","author":"Wang","year":"2025","journal-title":"IEEE Trans. Reliab."},{"key":"ref_73","doi-asserted-by":"crossref","first-page":"1731","DOI":"10.1109\/TCPMT.2024.3462818","article-title":"Robustness of Large-Size Vacuum Sealed Packages for Microbolometer Array","volume":"14","author":"Xia","year":"2024","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_74","first-page":"391","article-title":"An 11.6aF\/kPa Mechanical Stress Sensor with 0.808% Temperature-Drift Oscillator for Flip-Chip Packaging","volume":"70","author":"Xiao","year":"2023","journal-title":"IEEE Trans. Circuits Syst. II"},{"key":"ref_75","doi-asserted-by":"crossref","unstructured":"Rajmane, P., Dhandapani, K., Schwarz, M., and Syed, A. (July, January 1). Investigation of the Factors Affecting the Warpage Prediction of Multi-Chip Package. Proceedings of the 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, CA, USA.","DOI":"10.1109\/ECTC32696.2021.00240"},{"key":"ref_76","doi-asserted-by":"crossref","first-page":"150","DOI":"10.1109\/TCPMT.2024.3454639","article-title":"Innovating Semiconductor Packaging: Dynamic Finite Element Models and Steady-State Warpage Simulations","volume":"15","author":"Wu","year":"2025","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_77","doi-asserted-by":"crossref","first-page":"2016","DOI":"10.1109\/TCPMT.2023.3331692","article-title":"Development and Demonstration on Process-Oriented Warpage Simulation Methodology of Fan-Out Panel-Level Package in Multilevel Integration","volume":"13","author":"Lee","year":"2023","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_78","doi-asserted-by":"crossref","first-page":"5","DOI":"10.1109\/TCPMT.2019.2956325","article-title":"Process Modules for High-Density Interconnects in Panel-Level Packaging","volume":"10","author":"Schein","year":"2020","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_79","doi-asserted-by":"crossref","unstructured":"Zhao, X., Zheng, H., Zhao, Z., Cheng, M., Li, W., Wan, G., and Jia, Y. (2025). Warpage Prediction of Fan-out Wafer-Level Package Based on Coupled Deep Learning and Finite Element Simulation. Microelectron. Reliab., 170.","DOI":"10.1016\/j.microrel.2025.115759"},{"key":"ref_80","doi-asserted-by":"crossref","first-page":"1774","DOI":"10.1109\/TCPMT.2017.2707567","article-title":"Study on Low Warpage and High Reliability for Large Package Using TSV-Free Interposer Technology Through SMART Codesign Modeling","volume":"7","author":"Che","year":"2017","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_81","doi-asserted-by":"crossref","first-page":"730","DOI":"10.1109\/TCPMT.2020.2975571","article-title":"Study of Warpage Evolution and Control for Six-Side Molded WLCSP in Different Packaging Processes","volume":"10","author":"Qin","year":"2020","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_82","doi-asserted-by":"crossref","first-page":"112","DOI":"10.1109\/TDMR.2024.3352001","article-title":"Data-Driven Stress\/Warpage Analyses Based on Stoney Equation for Packaging Applications","volume":"24","author":"Chen","year":"2024","journal-title":"IEEE Trans. Device Mater. Relib."},{"key":"ref_83","doi-asserted-by":"crossref","first-page":"1601","DOI":"10.1109\/TCPMT.2024.3435835","article-title":"Investigation of Heat Dissipation and Electrical Properties of Diamond Interposer for 2.5-D Packagings","volume":"14","author":"Shi","year":"2024","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_84","doi-asserted-by":"crossref","unstructured":"Yang, X., Chen, H., Zhang, Y., Hou, T., Ren, P., Wang, R., Ji, Z., and Huang, R. (2025). Physics-Informed Learning Based Multiphysics Simulation for Fast Transient TSV Electromigration Analysis. ACM Trans. Des. Autom. Electron. Syst., 30.","DOI":"10.1145\/3706106"},{"key":"ref_85","doi-asserted-by":"crossref","first-page":"1385","DOI":"10.1109\/TCPMT.2025.3569685","article-title":"An Experimental Study on a Barrier-Less Cu Interconnect Scheme With Polyimide Insulator for Cost-Effective 3-D Packaging","volume":"15","author":"Wang","year":"2025","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_86","doi-asserted-by":"crossref","unstructured":"Wang, X., Yang, H., Cai, Y., and Li, N. (2024, January 28\u201330). Research on the Influence of Electrothermal Coupling on TSV Transmission Characteristics. Proceedings of the 2024 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Chengdu, China.","DOI":"10.1109\/RFIT60557.2024.10812380"},{"key":"ref_87","doi-asserted-by":"crossref","first-page":"2171","DOI":"10.1109\/TCPMT.2018.2853405","article-title":"High-Frequency Electrothermal Characterization of TSV-Based Power Delivery Network","volume":"8","author":"Li","year":"2018","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_88","doi-asserted-by":"crossref","first-page":"47","DOI":"10.1109\/LMWT.2024.3492341","article-title":"Compact Harmonic Suppression Low-Pass Filters With Stacked Dual RDL Structures Using 3-D Glass-Based Advanced Packaging Technology","volume":"35","author":"Zhang","year":"2025","journal-title":"IEEE Microw. Wirel. Tech. Lett."},{"key":"ref_89","unstructured":"Xie, R., Hong, W., Zhang, C., Lee, J., and Brew, K. (2024, January 16\u201320). Backside Power Distribution for Nanosheet Technologies beyond 2 nm. Proceedings of the IEEE\/JSAP Symposium on VLSI Technology and Circuits, Honolulu, HI, USA."},{"key":"ref_90","unstructured":"Lanzillo, N.A., Chu, A., Vega, R., Perez, N., Clevenger, L., and Dechene, D.J. (March, January 26). Methodology Development to Benchmark Power Delivery Designs in Advanced Technology Nodes. Proceedings of the SPIE Advanced Lithography + Patterning, San Jose, CA, USA."},{"key":"ref_91","doi-asserted-by":"crossref","first-page":"1235","DOI":"10.1109\/TCPMT.2021.3096148","article-title":"Near-Field Scanning Based Shielding Effectiveness Analysis of System in Package","volume":"11","author":"Ding","year":"2021","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_92","doi-asserted-by":"crossref","first-page":"1567","DOI":"10.1109\/TCPMT.2022.3198396","article-title":"Cost-Effective Surface-Mount Magnetoelectric Dipole Antenna Based on Ball Grid Array Packaging Technology for 5G Millimeter-Wave New Radio Band Applications","volume":"12","author":"Liu","year":"2022","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_93","doi-asserted-by":"crossref","first-page":"4267","DOI":"10.1109\/TED.2024.3405407","article-title":"Exploration and Analysis of Through-Glass Vias for High-Speed, Low-Loss Vertical Interconnects in Glass-Based 3-D Integrated Circuits","volume":"71","author":"Fang","year":"2024","journal-title":"IEEE Trans. Electron Devices"},{"key":"ref_94","doi-asserted-by":"crossref","unstructured":"Wang, C., Ren, P., Li, X., Liu, C., and Du, P. (2024, January 7\u20139). Coupling Characteristics of BGA Solder Balls at High Frequencies: A Simulation Study on Electromagnetic-Thermal-Mechanical Interactions Considering Skin and Proximity Effects. Proceedings of the 2024 25th International Conference on Electronic Packaging Technology (ICEPT), Tianjin, China.","DOI":"10.1109\/ICEPT63120.2024.10668627"},{"key":"ref_95","doi-asserted-by":"crossref","first-page":"1655","DOI":"10.1109\/TCPMT.2017.2737550","article-title":"Packaging of High-Gain Multichip Module in Multilayer LCP Substrates at $W$-Band","volume":"7","author":"Zhang","year":"2017","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_96","doi-asserted-by":"crossref","first-page":"1743","DOI":"10.1109\/TCPMT.2023.3321058","article-title":"A Polymer-Based Embedded Silicon Fan-Out Packaging (P-eSiFO) Method for High-Density Chiplet Packaging","volume":"13","author":"Chen","year":"2023","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_97","doi-asserted-by":"crossref","first-page":"552","DOI":"10.1109\/TCPMT.2017.2659700","article-title":"Design and Demonstration of a 2.5-D Glass Interposer BGA Package for High Bandwidth and Low Cost","volume":"7","author":"Sawyer","year":"2017","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."},{"key":"ref_98","doi-asserted-by":"crossref","unstructured":"Sharma, G., Rao, V.S., Kumar, A., Su, N., Ying, L.Y., Houe, K.C., Lim, S., Sekhar, V.N., Rajoo, R., and Kripesh, V. (2009, January 26\u201329). Embedded Wafer Level Packages with Laterally Placed and Vertically Stacked Thin Dies. Proceedings of the 2009 59th Electronic Components and Technology Conference, San Diego, CA, USA.","DOI":"10.1109\/ECTC.2009.5074217"},{"key":"ref_99","doi-asserted-by":"crossref","unstructured":"Chiang, Y.P., Tai, S.P., Wu, W.C., Yeh, J., Wang, C.T., and Yu, D.C.H. (July, January 1). InFO_oS (Integrated Fan-Out on Substrate) Technology for Advanced Chiplet Integration. Proceedings of the 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, CA, USA.","DOI":"10.1109\/ECTC32696.2021.00033"},{"key":"ref_100","doi-asserted-by":"crossref","unstructured":"Wudjud, W., Lin, S., Chang, Y., Yen, J., Liao, R., Cheng, L., Wu, Y., Huang, S.Y., Chen, J.T., and Lee, C. (2024, January 28\u201331). Advanced Thermocompression Bonding on High Density Fan-Out Embedded Bridge Technology for HPC\/AI\/ML Applications. Proceedings of the 2024 IEEE 74th Electronic Components and Technology Conference (ECTC), Denver, CO, USA.","DOI":"10.1109\/ECTC51529.2024.00151"},{"key":"ref_101","doi-asserted-by":"crossref","unstructured":"Braun, T., H\u00f6lck, O., Adler, M., Obst, M., Voges, S., Becker, K.-F., Aschenbrenner, R., Voitel, M., Dreissigacker, M., and Schneider-Ramelow, M. (2024, January 28\u201331). How to Manipulate Warpage in Fan-out Wafer and Panel Level Packaging. Proceedings of the 2024 IEEE 74th Electronic Components and Technology Conference (ECTC), Denver, CO, USA.","DOI":"10.1109\/ECTC51529.2024.00008"},{"key":"ref_102","unstructured":"UCIe Consortium (2026, August 04). UCIe 2.0 Specification: Advancing an Open Ecosystem for On-Package Chiplet Innovation. Available online: https:\/\/www.uciexpress.org\/specifications."},{"key":"ref_103","unstructured":"Intel Foundry (2026, August 04). Cutting-Edge Process Technologies for Data Center. Available online: https:\/\/www.intel.com\/content\/www\/us\/en\/foundry\/library\/advanced-process-technologies-for-data-center.html."},{"key":"ref_104","doi-asserted-by":"crossref","first-page":"291","DOI":"10.1109\/TCPMT.2023.3265568","article-title":"A Critical Review of Lithography Methodologies and Impacts of Topography on 2.5-D\/3-D Interposers","volume":"13","author":"Liu","year":"2023","journal-title":"IEEE Trans. Compon. Packag. Manuf. Technol."}],"container-title":["Micromachines"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2072-666X\/17\/9\/1039\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,8,31]],"date-time":"2026-08-31T02:16:16Z","timestamp":1788142576000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2072-666X\/17\/9\/1039"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,8,30]]},"references-count":104,"journal-issue":{"issue":"9","published-online":{"date-parts":[[2026,9]]}},"alternative-id":["mi17091039"],"URL":"https:\/\/doi.org\/10.3390\/mi17091039","relation":{},"ISSN":["2072-666X"],"issn-type":[{"value":"2072-666X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,8,30]]}}}