{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T19:35:20Z","timestamp":1782934520955,"version":"3.54.5"},"reference-count":169,"publisher":"MDPI AG","issue":"13","license":[{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"TCL science and technology innovation fund","award":["2025202"],"award-info":[{"award-number":["2025202"]}]},{"name":"Shenzhen Bureau of Science and Technology Research Fund","award":["KIZD20240903102708012"],"award-info":[{"award-number":["KIZD20240903102708012"]}]},{"DOI":"10.13039\/501100003453","name":"Natural Science Foundation of Guangdong","doi-asserted-by":"publisher","award":["no. 2024A1515012039"],"award-info":[{"award-number":["no. 2024A1515012039"]}],"id":[{"id":"10.13039\/501100003453","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Micro & Nano Electronics Platform (MNEP) of SCUT"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Nanomaterials"],"abstract":"<jats:p>Magnetoresistive random-access memory (MRAM), as a promising non-volatile memory technology, has attracted extensive research interest owing to its unique combination of high operating speed, exceptional endurance, low standby power consumption, and CMOS process compatibility. In this review, we provide a comprehensive overview of the technological evolution of MRAM, spanning from Toggle-MRAM to spin-transfer torque (STT)-MRAM and then to spin\u2013orbit torque (SOT)-MRAM. The working mechanisms, performance trade-offs, and integration potential of each generation are systematically summarized. Furthermore, the diverse applications of MRAM\u2014including embedded systems-on-chip (SoCs), edge computing, aerospace and automotive electronics, artificial intelligence accelerators, neuromorphic computing, and hardware-level security\u2014are thoroughly discussed. We also identify key challenges hindering large-scale commercialization, such as the trade-off between write energy and speed, process complexity, storage density constraints, and cost competitiveness. Finally, emerging research directions are proposed, emphasizing short-term priorities such as write current reduction and yield improvement, as well as long-term development strategies focusing on material\u2013device\u2013algorithm co-optimization and ecosystem establishment.<\/jats:p>","DOI":"10.3390\/nano16130816","type":"journal-article","created":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T16:50:33Z","timestamp":1782924633000},"page":"816","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["MRAM: A Versatile Non-Volatile Memory for Next-Generation Computing"],"prefix":"10.3390","volume":"16","author":[{"given":"Zhihan","family":"Wang","sequence":"first","affiliation":[{"name":"School of Microelectronics, South China University of Technology, Guangzhou 510641, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Haiwen","family":"Li","sequence":"additional","affiliation":[{"name":"School of Microelectronics, South China University of Technology, Guangzhou 510641, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0642-8203","authenticated-orcid":false,"given":"Sheng","family":"Jiang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, South China University of Technology, Guangzhou 510641, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"1968","published-online":{"date-parts":[[2026,7,1]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"McKee, S.A. (2004). Reflections on the Memory Wall. Proceedings of the 1st Conference on Computing Frontiers, Association for Computing Machinery.","DOI":"10.1145\/977091.977115"},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"20","DOI":"10.1145\/216585.216588","article-title":"Hitting the Memory Wall: Implications of the Obvious","volume":"23","author":"Wulf","year":"1995","journal-title":"SIGARCH Comput. Archit. News"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"1524","DOI":"10.1109\/TPDS.2014.2324563","article-title":"A Survey of Architectural Approaches for Managing Embedded DRAM and Non-Volatile On-Chip Caches","volume":"26","author":"Mittal","year":"2015","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"ref_4","unstructured":"Grupp, L.M., Davis, J.D., and Swanson, S. (2012). The Bleak Future of NAND Flash Memory. Proceedings of the 10th USENIX Conference on File and Storage Technologies, USENIX Association."},{"key":"ref_5","doi-asserted-by":"crossref","unstructured":"Stuecheli, J., Kaseridis, D., Hunter, H.C., and John, L.K. (2010). Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory. Proceedings of the 2010 43rd Annual IEEE\/ACM International Symposium on Microarchitecture, IEEE.","DOI":"10.1109\/MICRO.2010.22"},{"key":"ref_6","doi-asserted-by":"crossref","unstructured":"Nair, P., Chou, C.-C., and Qureshi, M.K. (2013). A Case for Refresh Pausing in DRAM Memory Systems. Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), IEEE.","DOI":"10.1109\/HPCA.2013.6522355"},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"305","DOI":"10.1109\/JPROC.2002.808156","article-title":"Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits","volume":"91","author":"Roy","year":"2003","journal-title":"Proc. IEEE"},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"162","DOI":"10.1016\/0040-6090(92)90888-I","article-title":"Magnetoresistive Memory Technology","volume":"216","author":"Daughton","year":"1992","journal-title":"Thin Solid. Film."},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"187","DOI":"10.1038\/nnano.2015.24","article-title":"A new spin on magnetic memories","volume":"10","author":"Kent","year":"2015","journal-title":"Nat. Nanotechnol."},{"key":"ref_10","doi-asserted-by":"crossref","unstructured":"Nozaki, T., Yamamoto, T., Miwa, S., Tsujikawa, M., Shirai, M., Yuasa, S., and Suzuki, Y. (2019). Recent Progress in the Voltage-Controlled Magnetic Anisotropy Effect and the Challenges Faced in Developing Voltage-Torque MRAM. Micromachines, 10.","DOI":"10.3390\/mi10050327"},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"868","DOI":"10.1038\/nmat1257","article-title":"Giant Room-Temperature Magnetoresistance in Single-Crystal Fe\/MgO\/Fe Magnetic Tunnel Junctions","volume":"3","author":"Yuasa","year":"2004","journal-title":"Nat. Mater."},{"key":"ref_12","doi-asserted-by":"crossref","first-page":"862","DOI":"10.1038\/nmat1256","article-title":"Giant Tunnelling Magnetoresistance at Room Temperature with MgO (100) Tunnel Barriers","volume":"3","author":"Parkin","year":"2004","journal-title":"Nat. Mater."},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"082508","DOI":"10.1063\/1.2976435","article-title":"Tunnel Magnetoresistance of 604% at 300K by Suppression of Ta Diffusion in CoFeB\/MgO\/CoFeB Pseudo-Spin-Valves Annealed at High Temperature","volume":"93","author":"Ikeda","year":"2008","journal-title":"Appl. Phys. Lett."},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"072503","DOI":"10.1063\/1.2012525","article-title":"Giant Tunneling Magnetoresistance Effect in Low-Resistance CoFeB\/MgO (001)\/CoFeB Magnetic Tunnel Junctions for Read-Head Applications","volume":"87","author":"Tsunekawa","year":"2005","journal-title":"Appl. Phys. Lett."},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"053003","DOI":"10.1143\/APEX.3.053003","article-title":"High Magnetoresistance Ratio and Low Resistance\u2013Area Product in Magnetic Tunnel Junctions with Perpendicularly Magnetized Electrodes","volume":"3","author":"Yakushiji","year":"2010","journal-title":"Appl. Phys. Express"},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"671","DOI":"10.1038\/s41467-018-03140-z","article-title":"Current-Induced Magnetization Switching in Atom-Thick Tungsten Engineered Perpendicular Magnetic Tunnel Junctions with Large Tunnel Magnetoresistance","volume":"9","author":"Wang","year":"2018","journal-title":"Nat. Commun."},{"key":"ref_17","doi-asserted-by":"crossref","first-page":"3104204","DOI":"10.1109\/LMAG.2016.2584582","article-title":"Perpendicular Magnetic Tunnel Junctions With Low Resistance-Area Product: High Output Voltage and Bias Dependence of Magnetoresistance","volume":"7","author":"Tezuka","year":"2016","journal-title":"IEEE Magn. Lett."},{"key":"ref_18","unstructured":"Peng, S.Z., Zhang, Y., Wang, M.X., Zhang, Y.G., and Zhao, W. (1999). Magnetic Tunnel Junctions for Spintronics: Principles and Applications. Wiley Encyclopedia of Electrical and Electronics Engineering, John Wiley & Sons."},{"key":"ref_19","doi-asserted-by":"crossref","first-page":"1398","DOI":"10.1109\/JPROC.2021.3084997","article-title":"Spintronics for Energy- Efficient Computing: An Overview and Outlook","volume":"109","author":"Guo","year":"2021","journal-title":"Proc. IEEE"},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"277","DOI":"10.1146\/annurev-matsci-082908-145355","article-title":"Materials for Magnetoresistive Random Access Memory","volume":"39","author":"Slaughter","year":"2009","journal-title":"Annu. Rev. Mater. Res."},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"021308","DOI":"10.1063\/5.0032538","article-title":"Recent Progress and Challenges in Magnetic Tunnel Junctions with 2D Materials for Spintronic Applications","volume":"8","author":"Zhang","year":"2021","journal-title":"Appl. Phys. Rev."},{"key":"ref_22","doi-asserted-by":"crossref","first-page":"1796","DOI":"10.1109\/JPROC.2016.2590142","article-title":"Magnetoresistive Random Access Memory","volume":"104","author":"Apalkov","year":"2016","journal-title":"Proc. IEEE"},{"key":"ref_23","doi-asserted-by":"crossref","first-page":"1407","DOI":"10.1109\/TED.2020.2965403","article-title":"Magnetoresistive Random Access Memory: Present and Future","volume":"67","author":"Ikegawa","year":"2020","journal-title":"IEEE Trans. Electron. Devices"},{"key":"ref_24","doi-asserted-by":"crossref","first-page":"054416","DOI":"10.1103\/PhysRevB.63.054416","article-title":"Spin-dependent tunneling conductance of Fe| MgO| Fe sandwiches","volume":"63","author":"Butler","year":"2001","journal-title":"Phys. Rev. B"},{"key":"ref_25","doi-asserted-by":"crossref","first-page":"220403","DOI":"10.1103\/PhysRevB.63.220403","article-title":"Theory of tunneling magnetoresistance of an epitaxial Fe\/MgO\/Fe (001) junction","volume":"63","author":"Mathon","year":"2001","journal-title":"Phys. Rev. B"},{"key":"ref_26","doi-asserted-by":"crossref","first-page":"9353","DOI":"10.1103\/PhysRevB.54.9353","article-title":"Emission of spin waves by a magnetic multilayer traversed by a current","volume":"54","author":"Berger","year":"1996","journal-title":"Phys. Rev. B"},{"key":"ref_27","doi-asserted-by":"crossref","first-page":"3273","DOI":"10.1103\/PhysRevLett.74.3273","article-title":"Large magnetoresistance at room temperature in ferromagnetic thin film tunnel junctions","volume":"74","author":"Moodera","year":"1995","journal-title":"Phys. Rev. Lett."},{"key":"ref_28","doi-asserted-by":"crossref","first-page":"132","DOI":"10.1109\/TMAG.2004.840847","article-title":"A 4-Mb toggle MRAM based on a novel bit and switching method","volume":"41","author":"Engel","year":"2005","journal-title":"IEEE Trans. Magn."},{"key":"ref_29","doi-asserted-by":"crossref","first-page":"352","DOI":"10.1557\/mrs.2018.93","article-title":"Materials for Spin-Transfer-Torque Magnetoresistive Random-Access Memory","volume":"43","author":"Yuasa","year":"2018","journal-title":"MRS Bull."},{"key":"ref_30","doi-asserted-by":"crossref","first-page":"025008","DOI":"10.1103\/RevModPhys.89.025008","article-title":"Perpendicular Magnetic Anisotropy at Transition Metal\/Oxide Interfaces and Applications","volume":"89","author":"Dieny","year":"2017","journal-title":"Rev. Mod. Phys."},{"key":"ref_31","doi-asserted-by":"crossref","first-page":"413","DOI":"10.1002\/pssr.201105420","article-title":"Materials with Perpendicular Magnetic Anisotropy for Magnetic Random Access Memory","volume":"5","author":"Sbiaa","year":"2011","journal-title":"Phys. Status Solidi RRL"},{"key":"ref_32","doi-asserted-by":"crossref","first-page":"730","DOI":"10.1038\/s44287-024-00111-z","article-title":"Spin-Transfer Torque Magnetoresistive Random Access Memory Technology Status and Future Directions","volume":"1","author":"Worledge","year":"2024","journal-title":"Nat. Rev. Electr. Eng."},{"key":"ref_33","doi-asserted-by":"crossref","first-page":"530","DOI":"10.1016\/j.mattod.2017.07.007","article-title":"Spintronics based random access memory: A review","volume":"20","author":"Bhatti","year":"2017","journal-title":"Mater. Today"},{"key":"ref_34","doi-asserted-by":"crossref","unstructured":"Lee, K., Bak, J.H., Kim, Y.J., Kim, C.K., Antonyan, A., Chang, D.H., Hwang, S.H., Lee, G.W., Ji, N.Y., and Kim, W.J. (2019). 1Gbit High Density Embedded STT-MRAM in 28nm FDSOI Technology. Proceedings of the 2019 IEEE International Electron Devices Meeting (IEDM), IEEE.","DOI":"10.1109\/IEDM19573.2019.8993551"},{"key":"ref_35","doi-asserted-by":"crossref","unstructured":"Lee, T.Y., Lee, J.M., Kim, M.K., Oh, J.S., Lee, J.W., Jeong, H.M., Jang, P.H., Joo, M.K., Suh, K., and Han, S.H. (2022). World-Most Energy-Efficient MRAM Technology for Non-Volatile RAM Applications. Proceedings of the 2022 International Electron Devices Meeting (IEDM), IEEE.","DOI":"10.1109\/IEDM45625.2022.10019430"},{"key":"ref_36","unstructured":"(2026, May 05). Everspin Launches a New Family of SPI Interface MRAM Products|MRAM-Info. Available online: https:\/\/www.mram-info.com\/everspin-launches-new-family-spi-interface-mram-products."},{"key":"ref_37","doi-asserted-by":"crossref","first-page":"189","DOI":"10.1038\/nature10309","article-title":"Perpendicular Switching of a Single Ferromagnetic Layer Induced by In-Plane Current Injection","volume":"476","author":"Miron","year":"2011","journal-title":"Nature"},{"key":"ref_38","doi-asserted-by":"crossref","first-page":"096602","DOI":"10.1103\/PhysRevLett.109.096602","article-title":"Current-Induced Switching of Perpendicularly Magnetized Magnetic Layers Using Spin Torque from the Spin Hall Effect","volume":"109","author":"Liu","year":"2012","journal-title":"Phys. Rev. Lett."},{"key":"ref_39","doi-asserted-by":"crossref","first-page":"555","DOI":"10.1126\/science.1218197","article-title":"Spin-Torque Switching with the Giant Spin Hall Effect of Tantalum","volume":"336","author":"Liu","year":"2012","journal-title":"Science"},{"key":"ref_40","doi-asserted-by":"crossref","first-page":"122404","DOI":"10.1063\/1.4753947","article-title":"Spin Transfer Torque Devices Utilizing the Giant Spin Hall Effect of Tungsten","volume":"101","author":"Pai","year":"2012","journal-title":"Appl. Phys. Lett."},{"key":"ref_41","doi-asserted-by":"crossref","first-page":"142403","DOI":"10.1063\/5.0022012","article-title":"Enhancement of Spin Hall Conductivity in W\u2013Ta Alloy","volume":"117","author":"Kim","year":"2020","journal-title":"Appl. Phys. Lett."},{"key":"ref_42","doi-asserted-by":"crossref","first-page":"240","DOI":"10.1038\/nmat3522","article-title":"Layer Thickness Dependence of the Current-Induced Effective Field Vector in Ta|CoFeB|MgO","volume":"12","author":"Kim","year":"2013","journal-title":"Nat. Mater."},{"key":"ref_43","doi-asserted-by":"crossref","first-page":"169692","DOI":"10.1016\/j.jmmm.2022.169692","article-title":"Spin-Orbit Torque Switching of Magnetic Tunnel Junctions for Memory Applications","volume":"562","author":"Krizakova","year":"2022","journal-title":"J. Magn. Magn. Mater."},{"key":"ref_44","doi-asserted-by":"crossref","first-page":"587","DOI":"10.1038\/nnano.2013.145","article-title":"Symmetry and Magnitude of Spin\u2013Orbit Torques in Ferromagnetic Heterostructures","volume":"8","author":"Garello","year":"2013","journal-title":"Nat. Nanotechnol."},{"key":"ref_45","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1038\/s41427-023-00521-9","article-title":"The Central Role of Tilted Anisotropy for Field-Free Spin\u2013Orbit Torque Switching of Perpendicular Magnetization","volume":"16","author":"Hu","year":"2024","journal-title":"NPG Asia Mater."},{"key":"ref_46","doi-asserted-by":"crossref","first-page":"3932","DOI":"10.1038\/s41467-023-39649-1","article-title":"Field-Free Spin-Orbit Torque Switching Assisted by In-Plane Unconventional Spin Torque in Ultrathin [Pt\/Co]N","volume":"14","author":"Xue","year":"2023","journal-title":"Nat. Commun."},{"key":"ref_47","doi-asserted-by":"crossref","first-page":"8722","DOI":"10.1038\/s41467-025-64109-3","article-title":"Tunable Unconventional Spin Orbit Torque Magnetization Dynamics in van der Waals Heterostructures","volume":"16","author":"Pandey","year":"2025","journal-title":"Nat. Commun."},{"key":"ref_48","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1038\/s44306-025-00071-6","article-title":"Field-Free Spin-Orbit Torques Switching and Its Applications","volume":"3","author":"Kang","year":"2025","journal-title":"npj Spintron."},{"key":"ref_49","doi-asserted-by":"crossref","first-page":"582","DOI":"10.1038\/s41928-018-0160-7","article-title":"Field-Free Switching of a Perpendicular Magnetic Tunnel Junction through the Interplay of Spin\u2013Orbit and Spin-Transfer Torques","volume":"1","author":"Wang","year":"2018","journal-title":"Nat. Electron."},{"key":"ref_50","doi-asserted-by":"crossref","first-page":"102501","DOI":"10.1088\/1674-4926\/43\/10\/102501","article-title":"Integration of High-Performance Spin-Orbit Torque MRAM Devices by 200-Mm-Wafer Manufacturing Platform","volume":"43","author":"Zhang","year":"2022","journal-title":"J. Semicond."},{"key":"ref_51","doi-asserted-by":"crossref","first-page":"122501","DOI":"10.1088\/1674-4926\/44\/12\/122501","article-title":"Demonstration of a Manufacturable SOT-MRAM Multiplexer Array towards Industrial Applications","volume":"44","author":"Jiang","year":"2023","journal-title":"J. Semicond."},{"key":"ref_52","doi-asserted-by":"crossref","first-page":"794","DOI":"10.1038\/s41928-025-01434-x","article-title":"A 64-Kilobit Spin\u2013Orbit Torque Magnetic Random-Access Memory Based on Back-End-of-Line-Compatible \u03b2-Tungsten","volume":"8","author":"Huang","year":"2025","journal-title":"Nat. Electron."},{"key":"ref_53","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2463585.2463589","article-title":"Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM)","volume":"9","author":"Apalkov","year":"2013","journal-title":"J. Emerg. Technol. Comput. Syst."},{"key":"ref_54","unstructured":"Durlam, M., Addie, D., Akerman, J., Butcher, B., Brown, P., Chan, J., DeHerrera, M., Engel, B.N., Feil, B., and Grynkewich, G. (2004). A 0.18\/Spl Mu\/m 4 Mbit Toggling MRAM. Proceedings of the 2004 International Conference on Integrated Circuit Design and Technology, IEEE."},{"key":"ref_55","doi-asserted-by":"crossref","unstructured":"Beach, R., Min, T., Horng, C., Chen, Q., Sherman, P., Le, S., Young, S., Yang, K., Yu, H., and Lu, X. (2008). A Statistical Study of Magnetic Tunnel Junctions for High-Density Spin Torque Transfer-MRAM (STT-MRAM). Proceedings of the 2008 IEEE International Electron Devices Meeting, IEEE.","DOI":"10.1109\/IEDM.2008.4796679"},{"key":"ref_56","doi-asserted-by":"crossref","unstructured":"Nebashi, R., Sakimura, N., Honjo, H., Saito, S., Ito, Y., Miura, S., Kato, Y., Mori, K., Ozaki, Y., and Kobayashi, Y. (2009). A 90nm 12ns 32Mb 2T1MTJ MRAM. Proceedings of the 2009 IEEE International Solid-State Circuits Conference\u2014Digest of Technical Papers, IEEE.","DOI":"10.1109\/ISSCC.2009.4977508"},{"key":"ref_57","doi-asserted-by":"crossref","unstructured":"Halupka, D., Huda, S., Song, W., Sheikholeslami, A., Tsunoda, K., Yoshida, C., and Aoki, M. (2010). Negative-Resistance Read and Write Schemes for STT-MRAM in 0.13 \u00b5m CMOS. Proceedings of the 2010 IEEE International Solid-State Circuits Conference\u2014(ISSCC), IEEE.","DOI":"10.1109\/ISSCC.2010.5433943"},{"key":"ref_58","doi-asserted-by":"crossref","unstructured":"Tsuchida, K., Inaba, T., Fujita, K., Ueda, Y., Shimizu, T., Asao, Y., Kajiyama, T., Iwayama, M., Sugiura, K., and Ikegawa, S. (2010). A 64Mb MRAM with Clamped-Reference and Adequate-Reference Schemes. Proceedings of the 2010 IEEE International Solid-State Circuits Conference\u2014(ISSCC), IEEE.","DOI":"10.1109\/ISSCC.2010.5433948"},{"key":"ref_59","doi-asserted-by":"crossref","unstructured":"Chung, S., Rho, K.-M., Kim, S.-D., Suh, H.-J., Kim, D.-J., Kim, H.-J., Lee, S.-H., Park, J.-H., Hwang, H.-M., and Hwang, S.-M. (2010). Fully Integrated 54nm STT-RAM with the Smallest Bit Cell Dimension for High Density Memory Application. Proceedings of the 2010 International Electron Devices Meeting, IEEE.","DOI":"10.1109\/IEDM.2010.5703351"},{"key":"ref_60","doi-asserted-by":"crossref","first-page":"869","DOI":"10.1109\/JSSC.2010.2040120","article-title":"A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and \u20181\u2019\/\u20180\u2019 Dual-Array Equalized Reference Scheme","volume":"45","author":"Takemura","year":"2010","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_61","doi-asserted-by":"crossref","unstructured":"Worledge, D.C., Hu, G., Trouilloud, P.L., Abraham, D.W., Brown, S., Gaidis, M.C., Nowak, J., O\u2019Sullivan, E.J., Robertazzi, R.P., and Sun, J.Z. (2010). Switching Distributions and Write Reliability of Perpendicular Spin Torque MRAM. Proceedings of the 2010 International Electron Devices Meeting, IEEE.","DOI":"10.1109\/IEDM.2010.5703349"},{"key":"ref_62","unstructured":"Kim, J.P., Kim, T., Hao, W., Rao, H.M., Lee, K., Zhu, X., Li, X., Hsu, W., Kang, S.H., and Matt, N. (2011). A 45nm 1Mb Embedded STT-MRAM with Design Techniques to Minimize Read-Disturbance. Proceedings of the 2011 Symposium on VLSI Circuits\u2014Digest of Technical Papers, IEEE."},{"key":"ref_63","doi-asserted-by":"crossref","unstructured":"Slaughter, J.M., Rizzo, N.D., Janesky, J., Whig, R., Mancoff, F.B., Houssameddine, D., Sun, J.J., Aggarwal, S., Nagel, K., and Deshpande, S. (2012). High Density ST-MRAM Technology (Invited). Proceedings of the 2012 International Electron Devices Meeting, IEEE.","DOI":"10.1109\/IEDM.2012.6479128"},{"key":"ref_64","unstructured":"Yu, H.-C., Lin, K.-C., Lin, K.-F., Huang, C.-Y., Chih, Y.-D., Ong, T.-C., Chang, J., Natarajan, S., and Tran, L.C. (2013). Cycling Endurance Optimization Scheme for 1Mb STT-MRAM in 40nm Technology. Proceedings of the 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, IEEE."},{"key":"ref_65","unstructured":"Ohsawa, T., Miura, S., Kinoshita, K., Honjo, H., Ikeda, S., Hanyu, T., Ohno, H., and Endoh, T. (2013). A 1.5nsec\/2.1nsec Random Read\/Write Cycle 1Mb STT-RAM Using 6T2MTJ Cell with Background Write for Nonvolatile e-Memories. Proceedings of the 2013 Symposium on VLSI Circuits, IEEE."},{"key":"ref_66","doi-asserted-by":"crossref","unstructured":"Lee, Y.J., Jan, G., Wang, Y.J., Pi, K., Zhong, T., Tong, R.Y., Lam, V., Teng, J., Huang, K., and He, R.R. (2013). Demonstration of Chip Level Writability, Endurance and Data Retention of an Entire 8Mb STT-MRAM Array. Proceedings of the 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), IEEE.","DOI":"10.1109\/VLSI-TSA.2013.6545595"},{"key":"ref_67","doi-asserted-by":"crossref","unstructured":"Kawasumi, A., Kushida, K., Hara, H., Unekawa, Y., Abe, K., Ikegami, K., Noguchi, H., Kitagawa, E., Kamata, C., and Kashiwada, S. (2013). Circuit Techniques in Realizing Voltage-Generator-Less STT MRAM Suitable for Normally-off-Type Non-Volatile L2 Cache Memory. Proceedings of the 2013 5th IEEE International Memory Workshop, IEEE.","DOI":"10.1109\/IMW.2013.6582102"},{"key":"ref_68","unstructured":"Noguchi, H., Kushida, K., Ikegami, K., Abe, K., Kitagawa, E., Kashiwada, S., Kamata, C., Kawasumi, A., Hara, H., and Fujita, S. (2013). A 250-MHz 256b-I\/O 1-Mb STT-MRAM with Advanced Perpendicular MTJ Based Dual Cell for Nonvolatile Magnetic Caches to Reduce Active Power of Processors. Proceedings of the 2013 Symposium on VLSI Technology, IEEE."},{"key":"ref_69","doi-asserted-by":"crossref","unstructured":"Jan, G., Thomas, L., Le, S., Lee, Y.-J., Liu, H., Zhu, J., Tong, R.-Y., Pi, K., Wang, Y.-J., and Shen, D. (2014). Demonstration of Fully Functional 8Mb Perpendicular STT-MRAM Chips with Sub-5ns Writing for Non-Volatile Embedded Memories. Proceedings of the 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, IEEE.","DOI":"10.1109\/VLSIT.2014.6894357"},{"key":"ref_70","doi-asserted-by":"crossref","unstructured":"DeBrosse, J., Maffitt, T., Nakamura, Y., Jan, G., and Wang, P.-K. (2015). A Fully-Functional 90nm 8Mb STT MRAM Demonstrator Featuring Trimmed, Reference Cell-Based Sensing. Proceedings of the 2015 IEEE Custom Integrated Circuits Conference (CICC), IEEE.","DOI":"10.1109\/CICC.2015.7338359"},{"key":"ref_71","doi-asserted-by":"crossref","unstructured":"Noguchi, H., Ikegami, K., Kushida, K., Abe, K., Itai, S., Takaya, S., Shimomura, N., Ito, J., Kawasumi, A., and Hara, H. (2015). 7.5 A 3.3ns-Access-Time 71.2\u03bcW\/MHz 1Mb Embedded STT-MRAM Using Physically Eliminated Read-Disturb Scheme and Normally-off Memory Architecture. Proceedings of the 2015 IEEE International Solid-State Circuits Conference\u2014(ISSCC) Digest of Technical Papers, IEEE.","DOI":"10.1109\/ISSCC.2015.7062963"},{"key":"ref_72","doi-asserted-by":"crossref","unstructured":"Noguchi, H., Ikegami, K., Takaya, S., Arima, E., Kushida, K., Kawasumi, A., Hara, H., Abe, K., Shimomura, N., and Ito, J. (2016). 7.2 4Mb STT-MRAM-Based Cache with Memory-Access-Aware Power Optimization and Write-Verify-Write\/Read-Modify-Write Scheme. Proceedings of the 2016 IEEE International Solid-State Circuits Conference (ISSCC), IEEE.","DOI":"10.1109\/ISSCC.2016.7417942"},{"key":"ref_73","doi-asserted-by":"crossref","unstructured":"Antonyan, A., Pyo, S., Jung, H., Koh, G.-H., and Song, T. (2017). 28-Nm 1T-1MTJ 8Mb 64 I\/O STT-MRAM with Symmetric 3-Section Reference Structure and Cross-Coupled Sensing Amplifier. Proceedings of the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE.","DOI":"10.1109\/ISCAS.2017.8050918"},{"key":"ref_74","doi-asserted-by":"crossref","unstructured":"Dong, Q., Wang, Z., Lim, J., Zhang, Y., Shih, Y.-C., Chih, Y.-D., Chang, J., Blaauw, D., and Sylvester, D. (2018). A 1Mb 28nm STT-MRAM with 2.8ns Read Access Time at 1.2V VDD Using Single-Cap Offset-Cancelled Sense Amplifier and in-Situ Self-Write-Termination. Proceedings of the 2018 IEEE International Solid-State Circuits Conference\u2014(ISSCC), IEEE.","DOI":"10.1109\/ISSCC.2018.8310393"},{"key":"ref_75","doi-asserted-by":"crossref","unstructured":"Aggarwal, S., Almasi, H., DeHerrera, M., Hughes, B., Ikegawa, S., Janesky, J., Lee, H.K., Lu, H., Mancoff, F.B., and Nagel, K. (2019). Demonstration of a Reliable 1 Gb Standalone Spin-Transfer Torque MRAM For Industrial Applications. Proceedings of the 2019 IEEE International Electron Devices Meeting (IEDM), IEEE.","DOI":"10.1109\/IEDM19573.2019.8993516"},{"key":"ref_76","doi-asserted-by":"crossref","unstructured":"Alzate, J.G., Arslan, U., Bai, P., Brockman, J., Chen, Y.J., Das, N., Fischer, K., Ghani, T., Heil, P., and Hentges, P. (2019). 2 MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications. Proceedings of the 2019 IEEE International Electron Devices Meeting (IEDM), IEEE.","DOI":"10.1109\/IEDM19573.2019.8993474"},{"key":"ref_77","doi-asserted-by":"crossref","unstructured":"Edwards, E.R.J., Hu, G., Brown, S.L., D\u2019Emic, C.P., Gottwald, M.G., Hashemi, P., Jung, H., Kim, J., Lauer, G., and Nowak, J.J. (2020). Demonstration of Narrow Switching Distributions in STTMRAM Arrays for LLC Applications at 1x Nm Node. Proceedings I have checked and revised allof the 2020 IEEE International Electron Devices Meeting (IEDM), IEEE.","DOI":"10.1109\/IEDM13553.2020.9371985"},{"key":"ref_78","doi-asserted-by":"crossref","unstructured":"Boujamaa, E.M., Ali, S.M., Wandji, S.N., Gourio, A., Pyo, S., Koh, G., Song, Y., Song, T., Kye, J., and Vial, J.C. (2020). A 14.7Mb\/Mm2 28nm FDSOI STT-MRAM with Current Starved Read Path, 52\u03a9\/Sigma Offset Voltage Sense Amplifier and Fully Trimmable CTAT Reference. Proceedings of the 2020 IEEE Symposium on VLSI Circuits, IEEE.","DOI":"10.1109\/VLSICircuits18222.2020.9162803"},{"key":"ref_79","doi-asserted-by":"crossref","first-page":"290","DOI":"10.1109\/ISSCC49657.2024.10454409","article-title":"15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB\/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs","volume":"Volume 67","author":"Ogawa","year":"2024","journal-title":"Proceedings of the 2024 IEEE International Solid-State Circuits Conference (ISSCC)"},{"key":"ref_80","doi-asserted-by":"crossref","first-page":"074001","DOI":"10.1088\/0022-3727\/46\/7\/074001","article-title":"Basic Principles of STT-MRAM Cell Operation in Memory Arrays","volume":"46","author":"Khvalkovskiy","year":"2013","journal-title":"J. Phys. D Appl. Phys."},{"key":"ref_81","doi-asserted-by":"crossref","first-page":"1634","DOI":"10.1109\/JPROC.2017.2697000","article-title":"Array Architectures for 3-D NAND Flash Memories","volume":"105","author":"Micheloni","year":"2017","journal-title":"Proc. IEEE"},{"key":"ref_82","doi-asserted-by":"crossref","unstructured":"Hsu, T.-H., Lue, H.-T., Hsu, P.-K., Yeh, T.-H., Du, P.-Y., Lee, G.-R., Chiu, C.-J., Wang, K.-C., and Lu, C.-Y. (2020). A Vertical Split-Gate Flash Memory Featuring High-Speed Source-Side Injection Programming, Read Disturb Free, and 100K Endurance for Embedded Flash (eFlash) Scaling and Computing-In-Memory (CIM). Proceedings of the 2020 IEEE International Electron Devices Meeting (IEDM), IEEE.","DOI":"10.1109\/IEDM13553.2020.9372036"},{"key":"ref_83","doi-asserted-by":"crossref","unstructured":"Horowitz, M. (2014). 1.1 Computing\u2019s Energy Problem (and What We Can Do about It). 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), IEEE.","DOI":"10.1109\/ISSCC.2014.6757323"},{"key":"ref_84","doi-asserted-by":"crossref","unstructured":"Hoefflinger, B. (2012). ITRS: The International Technology Roadmap for Semiconductors. Chips 2020: A Guide to the Future of Nanoelectronics, Springer.","DOI":"10.1007\/978-3-642-23096-7"},{"key":"ref_85","doi-asserted-by":"crossref","unstructured":"Antonyan, A., Pyo, S., Jung, H., and Song, T. (2018). Embedded MRAM Macro for eFlash Replacement. Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE.","DOI":"10.1109\/ISCAS.2018.8351201"},{"key":"ref_86","doi-asserted-by":"crossref","unstructured":"M\u00fcller, J., Pfefferling, B., Merbeth, T., Otani, Y., Hazen, D.S., Hula, T., Mansueto, M., Titova, A., Ramasubramanian, L., and Grimm, C.V.-B. (2024). Embedded STT-MRAM for Automotive Applications. Proceedings of the 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), IEEE.","DOI":"10.1109\/EDTM58488.2024.10511905"},{"key":"ref_87","doi-asserted-by":"crossref","unstructured":"Lee, Y.K., Song, Y., Kim, J., Oh, S., Bae, B.-J., Lee, S., Lee, J., Pi, U., Seo, B., and Jung, H. (2018). Embedded STT-MRAM in 28-Nm FDSOI Logic Process for Industrial MCU\/IoT Application. Proceedings of the 2018 IEEE Symposium on VLSI Technology, IEEE.","DOI":"10.1109\/VLSIT.2018.8510623"},{"key":"ref_88","doi-asserted-by":"crossref","first-page":"1256","DOI":"10.1109\/LED.2013.2279137","article-title":"R-MRAM: A ROM-Embedded STT MRAM Cache","volume":"34","author":"Lee","year":"2013","journal-title":"IEEE Electron. Device Lett."},{"key":"ref_89","doi-asserted-by":"crossref","first-page":"1283","DOI":"10.1109\/JSSC.2023.3314822","article-title":"A 22-Nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-Ns Random Read Access and 7.4-MB\/s Write Throughput at up to 150 \u00b0C","volume":"59","author":"Shimoi","year":"2024","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_90","doi-asserted-by":"crossref","first-page":"2360","DOI":"10.1109\/JSSC.2023.3236566","article-title":"TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge","volume":"58","author":"Jain","year":"2023","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_91","doi-asserted-by":"crossref","first-page":"295","DOI":"10.1109\/LSSC.2024.3465595","article-title":"A 14 Nm MRAM-Based Multi-Bit Analog In-Memory Computing With Process-Variation Calibration for 72 Macros-Based Accelerator","volume":"7","author":"Myung","year":"2024","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_92","doi-asserted-by":"crossref","first-page":"2070","DOI":"10.1109\/JSSC.2024.3386462","article-title":"A Fully Row\/Column-Parallel In-Memory Computing Macro in Foundry MRAM with Differential Readout for Noise Rejection","volume":"59","author":"Deaville","year":"2024","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_93","doi-asserted-by":"crossref","unstructured":"Qi, L., Fan, J., Cai, H., and Fang, Z. (2024). A Survey of Emerging Memory in a Microcontroller Unit. Micromachines, 15.","DOI":"10.3390\/mi15040488"},{"key":"ref_94","doi-asserted-by":"crossref","unstructured":"Lee, Y.-J., Cheng, C.-T., Huang, J.-C., Huang, K.-F., Lin, B.-H., Lin, B., Tseng, K.C., Jinnai, B., Tsai, M.-H., and Jiang, M.-R. (2025). Demonstration of Embedded MRAM with Sub-50 Nm MTJ for RAM-Like and MCU Applications. Proceedings of the 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE.","DOI":"10.23919\/VLSITechnologyandCir65189.2025.11075129"},{"key":"ref_95","doi-asserted-by":"crossref","unstructured":"Lee, T.Y., Lee, J.M., Oh, Y.W., Kim, H.-H., Kwon, B.S., Yamane, K., Kim, M.K., Jang, P.H., Lee, D.K., and Gwak, H.J. (2024). World-Most Energy-Efficient 14nm Automotive eMRAM Technology for High-Endurance Applications. Proceedings of the 2024 IEEE International Electron Devices Meeting (IEDM), IEEE.","DOI":"10.1109\/IEDM50854.2024.10873518"},{"key":"ref_96","first-page":"1","article-title":"Experimental Demonstration of STT-MRAM-Based Nonvolatile Instantly On\/Off System for IoT Applications: Case Studies","volume":"22","author":"Li","year":"2023","journal-title":"ACM Trans. Embed. Comput. Syst."},{"key":"ref_97","unstructured":"Sun, B., Liu, D., Yu, L., Li, J., Liu, H., Zhang, W., and Torng, T. (2018). MRAM Co-Designed Processing-in-Memory CNN Accelerator for Mobile and IoT Applications. arXiv, 2018."},{"key":"ref_98","doi-asserted-by":"crossref","first-page":"391","DOI":"10.1080\/00207217.2021.1908630","article-title":"Yanfeng Cache Performance of NV-STT-MRAM with Scale Effect and Comparison with SRAM","volume":"109","author":"Zhang","year":"2022","journal-title":"Int. J. Electron."},{"key":"ref_99","unstructured":"Jin, Y., Shihab, M., and Jung, M. (2014, January 14). Area, power, and latency considerations of STT-MRAM to substitute for main memory. In Proceedings of The Memory Forum, co-located with ISCA-41, Minneapolis, MN, USA."},{"key":"ref_100","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3490391","article-title":"Microarchitectural Exploration of STT-MRAM Last-Level Cache Parameters for Energy-Efficient Devices","volume":"21","author":"Marinelli","year":"2022","journal-title":"ACM Trans. Embed. Comput. Syst."},{"key":"ref_101","doi-asserted-by":"crossref","first-page":"167882","DOI":"10.1016\/j.jmmm.2021.167882","article-title":"Design of an Area and Energy-Efficient Last-Level Cache Memory Using STT-MRAM","volume":"529","author":"Aha","year":"2021","journal-title":"J. Magn. Magn. Mater."},{"key":"ref_102","doi-asserted-by":"crossref","first-page":"015058","DOI":"10.1063\/9.0000721","article-title":"Advanced Hybrid MRAM Based Novel GPU Cache System for Graphic Processing with High Efficiency","volume":"14","author":"Han","year":"2024","journal-title":"AIP Adv."},{"key":"ref_103","doi-asserted-by":"crossref","first-page":"455","DOI":"10.1109\/TC.2018.2875439","article-title":"TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches","volume":"68","author":"Cheshmikhani","year":"2019","journal-title":"IEEE Trans. Comput."},{"key":"ref_104","doi-asserted-by":"crossref","first-page":"3426","DOI":"10.1109\/TCAD.2021.3127148","article-title":"DeepNVM++: Cross-Layer Modeling and Optimization Framework of Nonvolatile Memories for Deep Learning","volume":"41","author":"Inci","year":"2022","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"ref_105","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1145\/3650729","article-title":"Toward Energy-Efficient STT-MRAM-Based Near Memory Computing Architecture for Embedded Systems","volume":"23","author":"Li","year":"2024","journal-title":"ACM Trans. Embed. Comput. Syst."},{"key":"ref_106","doi-asserted-by":"crossref","first-page":"1936","DOI":"10.1109\/JSSC.2021.3112182","article-title":"A 22-Nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB\/s Read Bandwidth for Security-Aware Mobile Device","volume":"57","author":"Chiu","year":"2022","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_107","doi-asserted-by":"crossref","first-page":"178","DOI":"10.1109\/ISSCC42614.2022.9731621","article-title":"A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB\/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS\/W 8b MAC for AI Operations","volume":"Volume 65","author":"Chiu","year":"2022","journal-title":"Proceedings of the 2022 IEEE International Solid-State Circuits Conference (ISSCC)"},{"key":"ref_108","doi-asserted-by":"crossref","first-page":"127","DOI":"10.1109\/JSSC.2021.3114881","article-title":"Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode","volume":"57","author":"Rossi","year":"2022","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_109","doi-asserted-by":"crossref","first-page":"390","DOI":"10.1109\/LSSC.2020.3024622","article-title":"A 1.02-\u03bcW STT-MRAM-Based DNN ECG Arrhythmia Monitoring SoC With Leakage-Based Delay MAC Unit","volume":"3","author":"Lee","year":"2020","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_110","doi-asserted-by":"crossref","unstructured":"Resch, S., Khatamifard, S.K., Chowdhury, Z.I., Zabihi, M., Zhao, Z., Cilasun, H., Wang, J.-P., Sapatnekar, S.S., and Karpuzcu, U.R. (2020). MOUSE: Inference In Non-Volatile Memory for Energy Harvesting Applications. Proceedings of the 2020 53rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), IEEE.","DOI":"10.1109\/MICRO50266.2020.00042"},{"key":"ref_111","doi-asserted-by":"crossref","unstructured":"Ranjan, A., Venkataramani, S., Pajouhi, Z., Venkatesan, R., Roy, K., and Raghunathan, A. (2017). STAxCache: An Approximate, Energy Efficient STT-MRAM Cache. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, IEEE.","DOI":"10.23919\/DATE.2017.7927016"},{"key":"ref_112","doi-asserted-by":"crossref","first-page":"414","DOI":"10.1109\/TC.2020.2989243","article-title":"NOSTalgy: Near-Optimum Run-Time STT-MRAM Quality-Energy Knob Management for Approximate Computing Applications","volume":"70","author":"Salahvarzi","year":"2021","journal-title":"IEEE Trans. Comput."},{"key":"ref_113","doi-asserted-by":"crossref","first-page":"4385","DOI":"10.1109\/TCAD.2020.2986320","article-title":"CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of Approximation","volume":"39","author":"Rahmani","year":"2020","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"ref_114","doi-asserted-by":"crossref","first-page":"470","DOI":"10.1109\/TVLSI.2017.2776954","article-title":"Computing in Memory With Spin-Transfer Torque Magnetic RAM","volume":"26","author":"Jain","year":"2018","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"ref_115","doi-asserted-by":"crossref","first-page":"155614","DOI":"10.1016\/j.aeue.2024.155614","article-title":"Stoch-IMC: A Bit-Parallel Stochastic in-Memory Computing Architecture Based on STT-MRAM","volume":"190","author":"Hajisadeghi","year":"2025","journal-title":"AEU-Int. J. Electron. Commun."},{"key":"ref_116","doi-asserted-by":"crossref","first-page":"28036","DOI":"10.1109\/ACCESS.2024.3365632","article-title":"Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey","volume":"12","author":"Yusuf","year":"2024","journal-title":"IEEE Access"},{"key":"ref_117","doi-asserted-by":"crossref","unstructured":"Deaville, P., Zhang, B., Chen, L.-Y., and Verma, N. (2021). A Maximally Row-Parallel MRAM In-Memory-Computing Macro Addressing Readout Circuit Sensitivity and Area. Proceedings of the ESSCIRC 2021\u2014IEEE 47th European Solid State Circuits Conference (ESSCIRC), IEEE.","DOI":"10.1109\/ESSCIRC53450.2021.9567807"},{"key":"ref_118","doi-asserted-by":"crossref","unstructured":"Wang, M., Yuan, Y., and Jiang, Y. (2023). Realization of Artificial Neurons and Synapses Based on STDP Designed by an MTJ Device. Micromachines, 14.","DOI":"10.3390\/mi14101820"},{"key":"ref_119","unstructured":"Zhou, P., Smith, J.A., Deremo, L., Heinrich-Barna, S.K., and Friedman, J.S. (2021). Synchronous Unsupervised STDP Learning with Stochastic STT-MRAM Switching. arXiv."},{"key":"ref_120","doi-asserted-by":"crossref","first-page":"7178","DOI":"10.1038\/s41598-022-11199-4","article-title":"Multi-State MRAM Cells for Hardware Neuromorphic Computing","volume":"12","author":"Rzeszut","year":"2022","journal-title":"Sci. Rep."},{"key":"ref_121","doi-asserted-by":"crossref","first-page":"142401","DOI":"10.1007\/s11432-021-3472-9","article-title":"NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration","volume":"66","author":"Zhao","year":"2023","journal-title":"Sci. China Inf. Sci."},{"key":"ref_122","doi-asserted-by":"crossref","first-page":"2816","DOI":"10.1109\/TC.2022.3155277","article-title":"SOT-MRAM Digital PIM Architecture With Extended Parallelism in Matrix Multiplication","volume":"71","author":"Kim","year":"2022","journal-title":"IEEE Trans. Comput."},{"key":"ref_123","doi-asserted-by":"crossref","first-page":"112128","DOI":"10.1016\/j.mee.2023.112128","article-title":"A Novel Time-Domain in-Memory Computing Unit Using STT-MRAM","volume":"284\u2013285","author":"Saha","year":"2024","journal-title":"Microelectron. Eng."},{"key":"ref_124","doi-asserted-by":"crossref","first-page":"144084","DOI":"10.1109\/ACCESS.2023.3344197","article-title":"SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing","volume":"11","author":"Moposita","year":"2023","journal-title":"IEEE Access"},{"key":"ref_125","doi-asserted-by":"crossref","unstructured":"Xie, W., Sang, H., Kalzhan, Z., Lee, J., Yoo, J., Lee, K., and Yoo, H.-J. (2025). Falcon: An Event-Driven Object Tracking SoC with Activation-Skip and Weight-Compression MRAM PIM and Heterogenous Q\/K\/V Read-Only-Once Attention Flow. Proceedings of the 2025 IEEE European Solid-State Electronics Research Conference (ESSERC), IEEE.","DOI":"10.1109\/ESSERC66193.2025.11214004"},{"key":"ref_126","first-page":"17:1","article-title":"Non-Volatile Processor Based on MRAM for Ultra-Low-Power IoT Devices","volume":"13","author":"Senni","year":"2016","journal-title":"J. Emerg. Technol. Comput. Syst."},{"key":"ref_127","doi-asserted-by":"crossref","first-page":"219","DOI":"10.1109\/JSSC.2023.3324335","article-title":"An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices","volume":"59","author":"You","year":"2024","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_128","unstructured":"Yuan, G., Ma, X., Lin, S., Li, Z., and Ding, C. (2019). A sot-mram-based processing-in-memory engine for highly compressed dnn implementation. arXiv."},{"key":"ref_129","doi-asserted-by":"crossref","first-page":"60","DOI":"10.1109\/ISSCC42613.2021.9365939","article-title":"4.4 A 1.3TOPS\/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7\u03bcW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode","volume":"Volume 64","author":"Rossi","year":"2021","journal-title":"Proceedings of the 2021 IEEE International Solid-State Circuits Conference (ISSCC)"},{"key":"ref_130","doi-asserted-by":"crossref","first-page":"2055","DOI":"10.1109\/JSSC.2024.3385987","article-title":"Siracusa: A 16 Nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine","volume":"59","author":"Prasad","year":"2024","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_131","doi-asserted-by":"crossref","first-page":"10220","DOI":"10.1038\/s41598-020-67257-2","article-title":"Immunity of Nanoscale Magnetic Tunnel Junctions with Perpendicular Magnetic Anisotropy to Ionizing Radiation","volume":"10","author":"Montoya","year":"2020","journal-title":"Sci. Rep."},{"key":"ref_132","first-page":"PC131191D","article-title":"Magneto-Resistive Random Access Memory (MRAM) for Space Applications","volume":"Volume PC13119","author":"Katti","year":"2024","journal-title":"Proceedings of the Spintronics XVII"},{"key":"ref_133","doi-asserted-by":"crossref","first-page":"491","DOI":"10.1109\/TVLSI.2018.2879439","article-title":"High-Entropy STT-MTJ-Based TRNG","volume":"27","author":"Vatajelu","year":"2019","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_134","doi-asserted-by":"crossref","first-page":"3400708","DOI":"10.1109\/TMAG.2025.3544442","article-title":"Temperature-Adaptive TRNG-Encrypted MRAM PUF: Enhancing Resistance to Machine Learning Attacks","volume":"61","author":"Dai","year":"2025","journal-title":"IEEE Trans. Magn."},{"key":"ref_135","doi-asserted-by":"crossref","first-page":"3510","DOI":"10.1109\/TVLSI.2025.3600042","article-title":"Dynamic Challenge Cross-Selection Physical Unclonable Function Based on MRAM","volume":"33","author":"Wu","year":"2025","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_136","doi-asserted-by":"crossref","first-page":"20649","DOI":"10.1038\/s41598-024-71730-7","article-title":"A Robust Deep Learning Attack Immune MRAM-Based Physical Unclonable Function","volume":"14","author":"Adel","year":"2024","journal-title":"Sci. Rep."},{"key":"ref_137","doi-asserted-by":"crossref","first-page":"2203558","DOI":"10.1002\/adma.202203558","article-title":"Spintronic Physical Unclonable Functions Based on Field-Free Spin\u2013Orbit-Torque Switching","volume":"34","author":"Lee","year":"2022","journal-title":"Adv. Mater."},{"key":"ref_138","doi-asserted-by":"crossref","first-page":"266","DOI":"10.1038\/nnano.2010.31","article-title":"Proposal for an All-Spin Logic Device with Built-in Memory","volume":"5","author":"Datta","year":"2010","journal-title":"Nat. Nanotechnol."},{"key":"ref_139","doi-asserted-by":"crossref","first-page":"3102604","DOI":"10.1109\/LMAG.2016.2539256","article-title":"Dependence of Voltage and Size on Write Error Rates in Spin-Transfer Torque Magnetic Random-Access Memory","volume":"7","author":"Nowak","year":"2016","journal-title":"IEEE Magn. Lett."},{"key":"ref_140","doi-asserted-by":"crossref","first-page":"1400210","DOI":"10.1109\/TMAG.2018.2799856","article-title":"Description of Statistical Switching in Perpendicular STT-MRAM Within an Analytical and Numerical Micromagnetic Framework","volume":"54","author":"Siracusano","year":"2018","journal-title":"IEEE Trans. Magn."},{"key":"ref_141","doi-asserted-by":"crossref","first-page":"721","DOI":"10.1038\/nmat2804","article-title":"A Perpendicular-Anisotropy CoFeB\u2013MgO Magnetic Tunnel Junction","volume":"9","author":"Ikeda","year":"2010","journal-title":"Nat. Mater."},{"key":"ref_142","doi-asserted-by":"crossref","first-page":"024016","DOI":"10.1103\/PhysRevApplied.19.024016","article-title":"Impact of Reference-Layer Stray Field on the Write-Error Rate of Perpendicular Spin-Transfer-Torque Random-Access Memory","volume":"19","author":"Nisar","year":"2023","journal-title":"Phys. Rev. Appl."},{"key":"ref_143","doi-asserted-by":"crossref","first-page":"813","DOI":"10.1038\/nmat2024","article-title":"The Emergence of Spin Electronics in Data Storage","volume":"6","author":"Chappert","year":"2007","journal-title":"Nat. Mater."},{"key":"ref_144","doi-asserted-by":"crossref","first-page":"035004","DOI":"10.1103\/RevModPhys.91.035004","article-title":"Current-Induced Spin-Orbit Torques in Ferromagnetic and Antiferromagnetic Systems","volume":"91","author":"Manchon","year":"2019","journal-title":"Rev. Mod. Phys."},{"key":"ref_145","doi-asserted-by":"crossref","unstructured":"Garello, K., Yasin, F., Couet, S., Souriau, L., Swerts, J., Rao, S., Van Beek, S., Kim, W., Liu, E., and Kundu, S. (2018). SOT-MRAM 300 mm Integration for Low Power and Ultrafast Embedded Memories. Proceedings of the 2018 IEEE Symposium on VLSI Circuits, IEEE.","DOI":"10.1109\/VLSIC.2018.8502269"},{"key":"ref_146","doi-asserted-by":"crossref","unstructured":"Cai, K., Talmelli, G., Fan, K., Van Beek, S., Kateel, V., Gupta, M., Monteiro Junior, M.G., Ben Chroud, M., Jayakumar, G., and Trovato, A. (2022). First Demonstration of Field-Free Perpendicular SOT-MRAM for Ultrafast and High-Density Embedded Memories. 2022 International Electron Devices Meeting (IEDM), IEEE.","DOI":"10.1109\/IEDM45625.2022.10019360"},{"key":"ref_147","doi-asserted-by":"crossref","unstructured":"Kawahara, T., Takemura, R., Miura, K., Hayakawa, J., Ikeda, S., Lee, Y., Sasaki, R., Goto, Y., Ito, K., and Meguro, T. (2007). 2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read. Proceedings of the 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, IEEE.","DOI":"10.1109\/ISSCC.2007.373503"},{"key":"ref_148","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1016\/j.sse.2016.07.006","article-title":"A Review of Emerging Non-Volatile Memory (NVM) Technologies and Applications","volume":"125","author":"Chen","year":"2016","journal-title":"Solid-State Electron."},{"key":"ref_149","doi-asserted-by":"crossref","unstructured":"Muller, G., Happ, T., Kund, M., Lee, G.Y., Nagel, N., and Sezi, R. (2004). Status and Outlook of Emerging Nonvolatile Memory Technologies. Proceedings of the IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004, IEEE.","DOI":"10.1109\/IEDM.2004.1419223"},{"key":"ref_150","doi-asserted-by":"crossref","first-page":"663","DOI":"10.1038\/s41467-018-03003-7","article-title":"Shape Anisotropy Revisited in Single-Digit Nanometer Magnetic Tunnel Junctions","volume":"9","author":"Watanabe","year":"2018","journal-title":"Nat. Commun."},{"key":"ref_151","doi-asserted-by":"crossref","first-page":"56","DOI":"10.1038\/s44306-024-00054-z","article-title":"Recent Progress on Controlling Spin\u2013Orbit Torques by Materials Design","volume":"2","author":"Ji","year":"2024","journal-title":"npj Spintron."},{"key":"ref_152","doi-asserted-by":"crossref","first-page":"031107","DOI":"10.1063\/1.5041793","article-title":"Recent Advances in Spin-Orbit Torques: Moving Towards Device Applications","volume":"5","author":"Ramaswamy","year":"2018","journal-title":"Appl. Phys. Rev."},{"key":"ref_153","doi-asserted-by":"crossref","first-page":"48","DOI":"10.1038\/s44306-024-00044-1","article-title":"Recent Progress in Spin-Orbit Torque Magnetic Random-Access Memory","volume":"2","author":"Nguyen","year":"2024","journal-title":"npj Spintron."},{"key":"ref_154","doi-asserted-by":"crossref","first-page":"130","DOI":"10.1038\/s41467-024-55437-x","article-title":"Harnessing Orbital Hall Effect in Spin-Orbit Torque MRAM","volume":"16","author":"Gupta","year":"2025","journal-title":"Nat. Commun."},{"key":"ref_155","doi-asserted-by":"crossref","first-page":"17","DOI":"10.1038\/s41699-020-0152-0","article-title":"2D Materials for Spintronic Devices","volume":"4","author":"Ahn","year":"2020","journal-title":"npj 2D Mater. Appl."},{"key":"ref_156","doi-asserted-by":"crossref","first-page":"6","DOI":"10.1038\/s44306-024-00011-w","article-title":"2D Magnetic Heterostructures: Spintronics and Quantum Future","volume":"2","author":"Zhang","year":"2024","journal-title":"npj Spintron."},{"key":"ref_157","doi-asserted-by":"crossref","first-page":"39","DOI":"10.1038\/s44306-025-00103-1","article-title":"Orbitronics in Two-Dimensional Materials","volume":"3","author":"Cysne","year":"2025","journal-title":"npj Spintron."},{"key":"ref_158","doi-asserted-by":"crossref","first-page":"19","DOI":"10.1038\/s44306-024-00023-6","article-title":"Spintronics Meets Orbitronics: Emergence of Orbital Angular Momentum in Solids","volume":"2","author":"Jo","year":"2024","journal-title":"npj Spintron."},{"key":"ref_159","doi-asserted-by":"crossref","first-page":"1113","DOI":"10.1557\/s43579-024-00673-x","article-title":"Van Der Waals Magnetic Materials for Current-Induced Control toward Spintronic Applications","volume":"14","author":"Ryu","year":"2024","journal-title":"MRS Commun."},{"key":"ref_160","doi-asserted-by":"crossref","unstructured":"Nguyen, T.V.A., Naganuma, H., Honjo, H., Sato, Y., Tanigawa, T., Ikeda, S., and Endoh, T. (2025). Low Write Power and Field-Free Sub-Ns Write Speed SOT-MRAM Cell with Design Technology of Canted SOT Structure and Magnetic Anisotropy for NVM. Proceedings of the 2025 IEEE International Memory Workshop (IMW), IEEE.","DOI":"10.1109\/IMW61990.2025.11026972"},{"key":"ref_161","doi-asserted-by":"crossref","first-page":"040902","DOI":"10.1063\/5.0135185","article-title":"Perspectives on Field-Free Spin-Orbit Torque Devices for Memory and Computing Applications","volume":"133","author":"Shao","year":"2023","journal-title":"J. Appl. Phys."},{"key":"ref_162","doi-asserted-by":"crossref","first-page":"022414","DOI":"10.1063\/1.4736727","article-title":"Perpendicular-Anisotropy CoFeB-MgO Magnetic Tunnel Junctions with a MgO\/CoFeB\/Ta\/CoFeB\/MgO Recording Structure","volume":"101","author":"Sato","year":"2012","journal-title":"Appl. Phys. Lett."},{"key":"ref_163","doi-asserted-by":"crossref","unstructured":"You, D.-Q., Khwa, W.-S., Wu, J.-J., Jhang, C.-J., Lin, G.-Y., Chen, P.-J., Chiu, T.-C., Chen, F.-Y., Lee, A., and Hung, Y.-C. (2024). A 22 nm Nonvolatile AI-Edge Processor with 21.4 TFLOPS\/W Using 47.25 Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro. 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE.","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631408"},{"key":"ref_164","doi-asserted-by":"crossref","unstructured":"Sun, X., Khwa, W.-S., Peng, X., Chang, M.-F., and Akarvardar, K. (2024). Non-Volatile Memory Technologies for Edge AI Applications. Proceedings of the 43rd IEEE\/ACM International Conference on Computer-Aided Design (ICCAD \u201824), ACM.","DOI":"10.1145\/3676536.3697115"},{"key":"ref_165","unstructured":"Roy, S., Wang, C., and Raghunathan, A. (2023). Evaluation of STT-MRAM as a Scratchpad for Training in ML Accelerators. arXiv."},{"key":"ref_166","doi-asserted-by":"crossref","first-page":"211","DOI":"10.1038\/s41586-021-04196-6","article-title":"A Crossbar Array of Magnetoresistive Memory Devices for In-Memory Computing","volume":"601","author":"Jung","year":"2022","journal-title":"Nature"},{"key":"ref_167","doi-asserted-by":"crossref","unstructured":"Bavikadi, S., Sutradhar, P.R., Khasawneh, K.N., Ganguly, A., and Dinakarrao, S.M.P. (2020). A Review of In-Memory Computing Architectures for Machine Learning Applications. GLSVLSI \u201820: Proceedings of the 2020 Great Lakes Symposium on VLSI, ACM.","DOI":"10.1145\/3386263.3407649"},{"key":"ref_168","doi-asserted-by":"crossref","first-page":"1046","DOI":"10.1038\/s41928-025-01479-y","article-title":"A Lossless and Fully Parallel Spintronic Compute-in-Memory Macro for Artificial Intelligence Chips","volume":"8","author":"Li","year":"2025","journal-title":"Nat. Electron."},{"key":"ref_169","doi-asserted-by":"crossref","first-page":"577","DOI":"10.1093\/nsr\/nwx082","article-title":"Memory That Never Forgets: Emerging Nonvolatile Memory and the Implication for Architecture Design","volume":"5","author":"Sun","year":"2018","journal-title":"Natl. Sci. Rev."}],"container-title":["Nanomaterials"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2079-4991\/16\/13\/816\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T17:48:19Z","timestamp":1782928099000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2079-4991\/16\/13\/816"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,7,1]]},"references-count":169,"journal-issue":{"issue":"13","published-online":{"date-parts":[[2026,7]]}},"alternative-id":["nano16130816"],"URL":"https:\/\/doi.org\/10.3390\/nano16130816","relation":{},"ISSN":["2079-4991"],"issn-type":[{"value":"2079-4991","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,7,1]]}}}