{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,10]],"date-time":"2025-10-10T01:04:32Z","timestamp":1760058272018,"version":"build-2065373602"},"reference-count":29,"publisher":"MDPI AG","issue":"6","license":[{"start":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T00:00:00Z","timestamp":1742342400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"French Agence Nationale de la Recherche","award":["ANR-21-CE39-0004"],"award-info":[{"award-number":["ANR-21-CE39-0004"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>Embedded systems can be targeted by fault injection attacks (FIAs), which enable attackers to alter the system specified behavior, potentially gaining access to confidential information or causing unintended outcomes, among other effects. Although numerous security sensors and attack detectors have been proposed in the literature to detect different sources of FIAs, it is crucial to ensure that these mechanisms themselves have not been tampered. Hence, the integrity of these detectors is critical in maintaining the security of embedded systems. This study focuses on evaluating the robustness of delay-based digital detectors against a new type of FIA called power-off temperature attack (POTA). POTA occurs when the chip power is turned off, rendering the detectors inactive and allowing the attackers to bypass them. After a POTA, the circuit or its detectors may not function properly when the power is restored, potentially allowing other attacks to go undetected if the detectors are less sensitive. This study implements two attack detectors on Xilinx Artix-7 FPGAs and investigates the impact of heating cycles on theses detectors\u2019 characteristics when the FPGA is in different states, including power-off, power-on, and inactive modes (such as clock-freezing mode). Our experiments reveal that heating cycles in power-off or inactive modes can alter the FPGA component delays and reduce the accuracy of its detectors, which highlights the vulnerability of these systems to POTA and potential risks to embedded system security.<\/jats:p>","DOI":"10.3390\/s25061912","type":"journal-article","created":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T06:10:53Z","timestamp":1742364653000},"page":"1912","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["On Power-Off Temperature Attacks Potential Against Security Sensors"],"prefix":"10.3390","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8058-0409","authenticated-orcid":false,"given":"Maryam","family":"Esmaeilian","sequence":"first","affiliation":[{"name":"LCIS, Grenoble INP, University Grenoble Alpes, 26000 Valence, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0617-3087","authenticated-orcid":false,"given":"Vincent","family":"Beroulle","sequence":"additional","affiliation":[{"name":"LCIS, Grenoble INP, University Grenoble Alpes, 26000 Valence, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3249-7667","authenticated-orcid":false,"given":"David","family":"H\u00e9ly","sequence":"additional","affiliation":[{"name":"LCIS, Grenoble INP, University Grenoble Alpes, 26000 Valence, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2025,3,19]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Kocher, P., Jaffe, J., and Jun, B. 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