{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,28]],"date-time":"2026-09-28T16:55:44Z","timestamp":1790614544290,"version":"4.1.0"},"reference-count":24,"publisher":"MDPI AG","issue":"19","license":[{"start":{"date-parts":[[2026,9,25]],"date-time":"2026-09-25T00:00:00Z","timestamp":1790294400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>Fractional output dividers (FODs) derive many clock domains from one integer-N phase-locked loop, but the gain error and integral nonlinearity (INL) of their digital-to-time converter (DTC) limit spectral purity. Existing FOD calibrations estimate the INL statistically, with no deterministic step count or residual bound. This paper presents a deterministic foreground calibration that measures the DTC bit weights in the delay domain. Reconfiguring an R-2R ladder bit by bit inside a constant-slope DTC maps each weight to a SAR-driven edge comparison against a replica chain, so the five mismatch-dominant weights are extracted inside a fixed 124-decision sequence and corrected through a 32-entry look-up table. Allocating one input period to discharge and N\u22121 periods to DAC settling enables a 10 GHz input. Exact conditions are derived for gain measurement, offset\u2013gain convergence, and weight extraction, together with the smooth curvature that per-bit calibration cannot observe. Transistor-level simulations in 22 nm FDSOI show chain tracking of 0.94 and offset\u2013gain convergence below half the 12.2 fs calibration step. A 200-die system-level Monte Carlo anchored to these statistics reduces the median peak INL from 4.1 to 0.32 LSB (24.4 fs LSB) and the worst fractional spur from \u221275.5 dBc to the \u221291 dBc quantization floor after 0.59 ms of calibration; the resulting 28 fs rms edge jitter permits 95 dB aperture-limited SNDR in a sampled sensor front end at 100 MHz.<\/jats:p>","DOI":"10.3390\/s26196091","type":"journal-article","created":{"date-parts":[[2026,9,25]],"date-time":"2026-09-25T14:36:34Z","timestamp":1790346994000},"page":"6091","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Deterministic Foreground Calibration of Gain and Integral Nonlinearity in Constant-Slope Digital-to-Time Converters for Fractional Output Dividers"],"prefix":"10.3390","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-6669-8812","authenticated-orcid":false,"given":"Saeid","family":"Karimpour","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA"}],"role":[{"vocabulary":"crossref","role":"author"},{"role":"conceptualization","vocabulary":"credit"},{"role":"methodology","vocabulary":"credit"},{"role":"software","vocabulary":"credit"},{"role":"validation","vocabulary":"credit"},{"role":"formal-analysis","vocabulary":"credit"},{"role":"writing-review-editing","vocabulary":"credit"},{"role":"writing-original-draft","vocabulary":"credit"},{"role":"data-curation","vocabulary":"credit"},{"role":"resources","vocabulary":"credit"},{"role":"investigation","vocabulary":"credit"},{"role":"visualization","vocabulary":"credit"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-8237-2384","authenticated-orcid":false,"given":"Emmanuel Nti","family":"Darko","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA"}],"role":[{"vocabulary":"crossref","role":"author"},{"role":"validation","vocabulary":"credit"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5938-6329","authenticated-orcid":false,"given":"Degang J.","family":"Chen","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"1968","published-online":{"date-parts":[[2026,9,25]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"2030","DOI":"10.1109\/JSSC.2025.3602127","article-title":"A Compact Low-Jitter All-Digital Fractional Output Divider Using Split-DTC-Based Background Calibration","volume":"61","author":"Luo","year":"2026","journal-title":"IEEE J. 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