{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T02:45:04Z","timestamp":1760150704090,"version":"build-2065373602"},"reference-count":31,"publisher":"MDPI AG","issue":"1","license":[{"start":{"date-parts":[[2023,12,25]],"date-time":"2023-12-25T00:00:00Z","timestamp":1703462400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100003593","name":"Brazil\u2019s National Council for Scientific and Technological Development (CNPq)","doi-asserted-by":"publisher","award":["120527\/2022-7"],"award-info":[{"award-number":["120527\/2022-7"]}],"id":[{"id":"10.13039\/501100003593","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Computers"],"abstract":"<jats:p>The growth of digital communications has driven the development of numerous cryptographic methods for secure data transfer and storage. The SHA-256 algorithm is a cryptographic hash function widely used for validating data authenticity, identity, and integrity. The inherent SHA-256 computational overhead has motivated the search for more efficient hardware solutions, such as application-specific integrated circuits (ASICs). This work presents a custom ASIC hardware accelerator for the SHA-256 algorithm entirely created using open-source electronic design automation tools. The integrated circuit was synthesized using SkyWater SKY130 130 nm process technology through the OpenLANE automated workflow. The proposed final design is compatible with 32-bit microcontrollers, has a total area of 104,585 \u00b5m2, and operates at a maximum clock frequency of 97.9 MHz. Several optimization configurations were tested and analyzed during the synthesis phase to enhance the performance of the final design.<\/jats:p>","DOI":"10.3390\/computers13010009","type":"journal-article","created":{"date-parts":[[2023,12,25]],"date-time":"2023-12-25T03:42:12Z","timestamp":1703475732000},"page":"9","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Custom ASIC Design for SHA-256 Using Open-Source Tools"],"prefix":"10.3390","volume":"13","author":[{"ORCID":"https:\/\/orcid.org\/0009-0006-7236-7188","authenticated-orcid":false,"given":"Lucas Daudt","family":"Franck","sequence":"first","affiliation":[{"name":"Group of Metamaterials Microwaves and Optics (GMeta), Department of Electrical Engineering (SEL), University of S\u00e3o Paulo (USP), Avenida Trabalhador S\u00e3o-Carlense, Nr. 400, Parque Industrial Arnold Schimidt, S\u00e3o Carlos 13566-590, SP, Brazil"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1021-0701","authenticated-orcid":false,"given":"Gabriel Augusto","family":"Ginja","sequence":"additional","affiliation":[{"name":"Group of Metamaterials Microwaves and Optics (GMeta), Department of Electrical Engineering (SEL), University of S\u00e3o Paulo (USP), Avenida Trabalhador S\u00e3o-Carlense, Nr. 400, Parque Industrial Arnold Schimidt, S\u00e3o Carlos 13566-590, SP, Brazil"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7955-7503","authenticated-orcid":false,"given":"Jo\u00e3o Paulo","family":"Carmo","sequence":"additional","affiliation":[{"name":"Group of Metamaterials Microwaves and Optics (GMeta), Department of Electrical Engineering (SEL), University of S\u00e3o Paulo (USP), Avenida Trabalhador S\u00e3o-Carlense, Nr. 400, Parque Industrial Arnold Schimidt, S\u00e3o Carlos 13566-590, SP, Brazil"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6275-9467","authenticated-orcid":false,"given":"Jos\u00e9 A.","family":"Afonso","sequence":"additional","affiliation":[{"name":"CMEMS-UMinho, University of Minho, 4800-058 Guimar\u00e3es, Portugal"},{"name":"LABBELS\u2014Associate Laboratory, University of Minho, 4710-057 Braga, Portugal"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7419-2154","authenticated-orcid":false,"given":"Maximiliam","family":"Luppe","sequence":"additional","affiliation":[{"name":"Group of Metamaterials Microwaves and Optics (GMeta), Department of Electrical Engineering (SEL), University of S\u00e3o Paulo (USP), Avenida Trabalhador S\u00e3o-Carlense, Nr. 400, Parque Industrial Arnold Schimidt, S\u00e3o Carlos 13566-590, SP, Brazil"}]}],"member":"1968","published-online":{"date-parts":[[2023,12,25]]},"reference":[{"key":"ref_1","unstructured":"Andrews, W., and Lindeman, T. (2023, February 23). The Black Budget. Available online: https:\/\/www.washingtonpost.com\/wp-srv\/special\/national\/black-budget\/."},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Rawal, B.S., Kumar, L.S., Maganti, S., and Godha, V. (2022, January 6\u20139). Comparative Study of Sha-256 Optimization Techniques. Proceedings of the 2022 IEEE World AI IoT Congress (AIIoT), Seattle, WA, USA.","DOI":"10.1109\/AIIoT54504.2022.9817185"},{"key":"ref_3","unstructured":"(2015). Secure Hash Standard (SHS) (Standard No. FIPS 180-4)."},{"key":"ref_4","doi-asserted-by":"crossref","unstructured":"Zhang, X., Liu, B., Zhao, Y., Hu, X., Shen, Z., Zheng, Z., Liu, Z., Chong, K.-S., Yu, G., and Wang, C. (2022). Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices. Sensors, 22.","DOI":"10.3390\/s22239160"},{"key":"ref_5","doi-asserted-by":"crossref","unstructured":"Sghaier, A., Zeghid, M., Massoud, C., and Mahchout, M. (2017). Design And Implementation of Low Area\/Power Elliptic Curve Digital Signature Hardware Core. Electronics, 6.","DOI":"10.3390\/electronics6020046"},{"key":"ref_6","doi-asserted-by":"crossref","unstructured":"Diehl, W., Abdulgadir, A., Kaps, J.-P., and Gaj, K. (2018). Comparing the Cost of Protecting Selected Lightweight Block Ciphers against Differential Power Analysis in Low-Cost FPGAs. Computers, 7.","DOI":"10.3390\/computers7020028"},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Nam, H., and Lysecky, R. (2018). Mixed Cryptography Constrained Optimization for Heterogeneous, Multicore, and Distributed Embedded Systems. Computers, 7.","DOI":"10.3390\/computers7020029"},{"key":"ref_8","doi-asserted-by":"crossref","unstructured":"Baldanzi, L., Crocetti, L., Falaschi, F., Bertolucci, M., Belli, J., Fanucci, L., and Saponara, S. (2020). Cryptographically Secure Pseudo-Random Number Generator IP-Core Based on SHA2 Algorithm. Sensors, 20.","DOI":"10.3390\/s20071869"},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"Zhu, S., Zhu, C., and Wang, W. (2018). A New Image Encryption Algorithm Based on Chaos and Secure Hash SHA-256. Entropy, 20.","DOI":"10.3390\/e20090716"},{"key":"ref_10","doi-asserted-by":"crossref","unstructured":"Xu, W., Xu, Y., Huo, G., Yang, Y., and Jin, Y. (2022, January 23\u201324). Optimized Dual-mode Security Encryption Chip Design Based on Hash Algorithm. Proceedings of the 2022 IEEE 11th International Conference on Communication Systems and Network Technologies (CSNT), Indore, India.","DOI":"10.1109\/CSNT54456.2022.9787655"},{"key":"ref_11","doi-asserted-by":"crossref","unstructured":"Dadda, L., Macchetti, M., and Owen, J. (2004, January 16\u201320). The design of a high speed ASIC unit for the hash function SHA-256 (384, 512). Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Paris, France.","DOI":"10.1145\/988952.989053"},{"key":"ref_12","unstructured":"Bai, L., and Li, S. (2009, January 20\u201323). VLSI implementation of high-speed SHA-256. Proceedings of the 2009 IEEE 8th International Conference on ASIC, Changsha, China."},{"key":"ref_13","doi-asserted-by":"crossref","unstructured":"Wu, R., Zhang, X., Wang, M., and Wang, L. (2020, January 16\u201319). A High-Performance Parallel Hardware Architecture of SHA-256 Hash in ASIC. Proceedings of the 2020 22nd International Conference on Advanced Communication Technology (ICACT), Phoenix Park, Republic of Korea.","DOI":"10.23919\/ICACT48636.2020.9061457"},{"key":"ref_14","doi-asserted-by":"crossref","unstructured":"Li, J., He, Z., and Qin, Y. (November, January 30). Design of Asynchronous High Throughput SHA-256 Hardware Accelerator in 40nm CMOS. Proceedings of the 2019 IEEE 13th International Conference on ASIC (ASICON), Chongqing, China.","DOI":"10.1109\/ASICON47005.2019.8983530"},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"1553","DOI":"10.1109\/TCSI.2021.3054758","article-title":"A New Message Expansion Structure for Full Pipeline SHA-2","volume":"68","author":"Zhang","year":"2021","journal-title":"IEEE Trans. Circuits Syst. Regul. Pap."},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"103444","DOI":"10.1016\/j.micpro.2020.103444","article-title":"SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative","volume":"87","author":"Nannipieri","year":"2020","journal-title":"Microprocess Microsyst."},{"key":"ref_17","unstructured":"Le, V.T.D., Pham, H.L., Duong, T.S., Tran, T.H., Nguyen, Q.D.N., and Nakashima, Y. (2023, January 18\u201320). RHCP: A Reconfigurable High-efficient Cryptographic Processor for Decentralized IoT Platforms. Proceedings of the 2023 15th International Conference on Knowledge and Systems Engineering (KSE), Hanoi, Vietnam."},{"key":"ref_18","doi-asserted-by":"crossref","first-page":"227","DOI":"10.1016\/j.micpro.2016.05.011","article-title":"Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions\u2019 architectures","volume":"45","author":"Michail","year":"2016","journal-title":"Microprocess Microsyst."},{"key":"ref_19","doi-asserted-by":"crossref","unstructured":"Shalan, M., and Edwards, T. (2020, January 2\u20135). Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow: Invited Paper. Proceedings of the 2020 IEEE\/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA.","DOI":"10.1145\/3400302.3415735"},{"key":"ref_20","unstructured":"LDFranck (2023, November 01). Custom ASIC Design for SHA-256 GitHub. Available online: https:\/\/github.com\/LDFranck\/SHA-256."},{"key":"ref_21","unstructured":"D\u2019Amore, R. (2005). VHDL Descri\u00e7\u00e3o e S\u00edntese de Circuitos Digitais, LTC. [2nd ed.]."},{"key":"ref_22","unstructured":"Balaji, S. (2020). Digital Design Flow Techniques and Circuit Design for Thin-Film Transistors. [Master\u2019s Thesis, Lund University]."},{"key":"ref_23","unstructured":"(2023, November 01). The OpenROAD Project. Available online: https:\/\/theopenroadproject.org\/."},{"key":"ref_24","unstructured":"YosysHQ (2023, November 01). Yosys Open Synthesis Suite GitHub. Available online: https:\/\/github.com\/YosysHQ\/yosys."},{"key":"ref_25","unstructured":"RTimothyEdwards (2023, November 01). Magic GitHub. Available online: https:\/\/github.com\/RTimothyEdwards\/magic."},{"key":"ref_26","unstructured":"RTimothyEdwards (2023, November 01). Netgen GitHub. Available online: https:\/\/github.com\/RTimothyEdwards\/netgen."},{"key":"ref_27","unstructured":"(2023, November 01). KLayout EDA Tool. Available online: https:\/\/www.klayout.de\/."},{"key":"ref_28","unstructured":"SkyWater Foundries (2023, August 06). FOSS 130 nm Production PDK. Available online: https:\/\/skywater-pdk.readthedocs.io\/."},{"key":"ref_29","unstructured":"Efabless Corporation (2023, August 06). OpenLANE Project GitHub. Available online: https:\/\/github.com\/The-OpenROAD-Project\/OpenLane."},{"key":"ref_30","unstructured":"Martin, D. (2023, March 02). SHA-256 Algorithm Explained. Available online: https:\/\/sha256algorithm.com\/."},{"key":"ref_31","unstructured":"Efabless Corporation (2023, August 06). The OpenLANE Documentation. Available online: https:\/\/openlane.readthedocs.io\/."}],"container-title":["Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2073-431X\/13\/1\/9\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,10]],"date-time":"2025-10-10T21:41:32Z","timestamp":1760132492000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2073-431X\/13\/1\/9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,12,25]]},"references-count":31,"journal-issue":{"issue":"1","published-online":{"date-parts":[[2024,1]]}},"alternative-id":["computers13010009"],"URL":"https:\/\/doi.org\/10.3390\/computers13010009","relation":{},"ISSN":["2073-431X"],"issn-type":[{"type":"electronic","value":"2073-431X"}],"subject":[],"published":{"date-parts":[[2023,12,25]]}}}