{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,16]],"date-time":"2026-01-16T07:15:28Z","timestamp":1768547728295,"version":"3.49.0"},"reference-count":47,"publisher":"MDPI AG","issue":"6","license":[{"start":{"date-parts":[[2021,3,12]],"date-time":"2021-03-12T00:00:00Z","timestamp":1615507200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Electronics"],"abstract":"<jats:p>Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations.<\/jats:p>","DOI":"10.3390\/electronics10060669","type":"journal-article","created":{"date-parts":[[2021,3,12]],"date-time":"2021-03-12T11:56:55Z","timestamp":1615550215000},"page":"669","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":8,"title":["Coarse-Grained Reconfigurable Computing with the Versat Architecture"],"prefix":"10.3390","volume":"10","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8903-9715","authenticated-orcid":false,"given":"Jo\u00e3o D.","family":"Lopes","sequence":"first","affiliation":[{"name":"INESC-ID, Instituto Superior T\u00e9cnico, Universidade de Lisboa, 1049-001 Lisbon, Portugal"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8556-4507","authenticated-orcid":false,"given":"M\u00e1rio P.","family":"V\u00e9stias","sequence":"additional","affiliation":[{"name":"INESC-ID, Instituto Superior de Engenharia de Lisboa, Instituto Polit\u00e9cnico de Lisboa, 1959-007 Lisbon, Portugal"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7060-4745","authenticated-orcid":false,"given":"Rui Policarpo","family":"Duarte\u00a0","sequence":"additional","affiliation":[{"name":"INESC-ID, Instituto Superior T\u00e9cnico, Universidade de Lisboa, 1049-001 Lisbon, Portugal"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3621-8322","authenticated-orcid":false,"given":"Hor\u00e1cio C.","family":"Neto","sequence":"additional","affiliation":[{"name":"INESC-ID, Instituto Superior T\u00e9cnico, Universidade de Lisboa, 1049-001 Lisbon, Portugal"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7525-7546","authenticated-orcid":false,"given":"Jos\u00e9 T.","family":"de Sousa\u00a0","sequence":"additional","affiliation":[{"name":"INESC-ID, Instituto Superior T\u00e9cnico, Universidade de Lisboa, 1049-001 Lisbon, Portugal"}]}],"member":"1968","published-online":{"date-parts":[[2021,3,12]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Bhattacharyya, S.S., Deprettere, E.F., Leupers, R., and Takala, J. (2010). Coarse-Grained Reconfigurable Array Architectures. Handbook of Signal Processing Systems, Springer.","DOI":"10.1007\/978-1-4419-6345-1"},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Qiu, J., Wang, J., Yao, S., Guo, K., Li, B., Zhou, E., Yu, J., Tang, T., Xu, N., and Song, S. (2016, January 22). Going Deeper with Embedded FPGA Platform for Convolutional Neural Network. Proceedings of the 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA\u201916), Monterey, CA, USA.","DOI":"10.1145\/2847263.2847265"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"147","DOI":"10.1023\/A:1008189221436","article-title":"Design and Implementation of the MorphoSys Reconfigurable Computing Processor","volume":"24","author":"Singh","year":"2000","journal-title":"J. Vlsi Signal-Process. Syst. Signal Image Video Technol."},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1109\/MDT.2005.27","article-title":"Architecture exploration for a reconfigurable architecture template","volume":"22","author":"Mei","year":"2005","journal-title":"Des. Test Comput."},{"key":"ref_5","doi-asserted-by":"crossref","unstructured":"Estrin, G. (1960). Organization of Computer Systems: The Fixed plus Variable Structure Computer. Papers Presented at the May 3\u20135, 1960, Western Joint IRE-AIEE-ACM Computer Conference, Association for Computing Machinery. IRE-AIEE-ACM\u201960 (Western).","DOI":"10.1145\/1460361.1460365"},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"975","DOI":"10.1109\/4.92017","article-title":"A novel ASIC design approach based on a new machine paradigm","volume":"26","author":"Hartenstein","year":"1991","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"1895","DOI":"10.1109\/4.173120","article-title":"A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths","volume":"27","author":"Chen","year":"1992","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_8","first-page":"1","article-title":"Article: Survey on Coarse Grained Reconfigurable Architectures","volume":"48","author":"Tehre","year":"2012","journal-title":"Int. J. Comput. Appl."},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"Wijtvliet, M., Waeijen, L., and Corporaal, H. (2016, January 17\u201321). Coarse grained reconfigurable architectures in the past 25 years: Overview and classification. Proceedings of the 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Agios Konstantinos, Greece.","DOI":"10.1109\/SAMOS.2016.7818353"},{"key":"ref_10","doi-asserted-by":"crossref","unstructured":"Liu, L., Zhu, J., Li, Z., Lu, Y., Deng, Y., Han, J., Yin, S., and Wei, S. (2019). A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications. ACM Comput. Surv., 52.","DOI":"10.1145\/3357375"},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"146719","DOI":"10.1109\/ACCESS.2020.3012084","article-title":"A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective","volume":"8","author":"Podobas","year":"2020","journal-title":"IEEE Access"},{"key":"ref_12","unstructured":"Hauser, J.R., and Wawrzynek, J. (1997, January 16\u201318). Garp: A MIPS processor with a reconfigurable coprocessor. Proceedings of the 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186, Napa Valley, CA, USA."},{"key":"ref_13","doi-asserted-by":"crossref","unstructured":"Marshall, A., Stansfield, T., Kostarnov, I., Vuillemin, J., and Hutchings, B. (1999, January 22). A Reconfigurable Arithmetic Array for Multimedia Applications. Proceedings of the 1999 ACM\/SIGDA Seventh International Symposium on Field Programmable Gate Arrays (FPGA \u201999), Monterey, CA, USA.","DOI":"10.1145\/296399.296444"},{"key":"ref_14","unstructured":"Agarwal, A., Amarasinghe, S., Barua, R., Frank, M., Lee, W., Sarkar, V., Srikrishna, D., and Taylor, M. (1997, January 21\u201323). The Raw Compiler Project. Proceedings of the Second SUIF Compiler Workshop, Stanford, CA, USA."},{"key":"ref_15","doi-asserted-by":"crossref","unstructured":"Hartenstein, R.W., and Serv\u00edt, M.Z. (1994). A new FPGA architecture for word-oriented datapaths. Field-Programmable Logic Architectures, Synthesis and Applications, Springer.","DOI":"10.1007\/3-540-58419-6"},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/2.839324","article-title":"PipeRench: A reconfigurable architecture and compiler","volume":"33","author":"Goldstein","year":"2000","journal-title":"Computer"},{"key":"ref_17","unstructured":"De Hon, M. (1996, January 17\u201319). MATRIX: A reconfigurable computing architecture with configurable instruction distribution and deployable resources. Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA, USA."},{"key":"ref_18","unstructured":"Miyamori, T., and Olukotun, K. (2021, March 05). REMARC: Reconfigurable Multimedia Array Coprocessor. IEICE Transactions on Information and Systems. Available online: https:\/\/citeseerx.ist.psu.edu\/viewdoc\/download?doi=10.1.1.64.6917&rep=rep1&type=pdf."},{"key":"ref_19","doi-asserted-by":"crossref","unstructured":"Amestoy, P., Berger, P., Dayd\u00e9, M., Ruiz, D., Duff, I., Frayss\u00e9, V., and Giraud, L. (1999). The MorphoSys Parallel Reconfigurable System. Euro-Par\u201999 Parallel Processing, Springer.","DOI":"10.1007\/3-540-48311-X"},{"key":"ref_20","doi-asserted-by":"crossref","unstructured":"Cheung, P., and Constantinides, G.A. (2003). ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. Field Programmable Logic and Application, Springer.","DOI":"10.1007\/b12007"},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"44","DOI":"10.1109\/MC.2004.65","article-title":"Scaling to the end of silicon with EDGE architectures","volume":"37","author":"Burger","year":"2004","journal-title":"Computer"},{"key":"ref_22","doi-asserted-by":"crossref","unstructured":"Chalamalasetti, S.R., Purohit, S., Margala, M., and Vanderbauwhede, W. (August, January 29). MORA\u2014An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor. Proceedings of the 2009 NASA\/ESA Conference on Adaptive Hardware and Systems, San Francisco, CA, USA.","DOI":"10.1109\/AHS.2009.37"},{"key":"ref_23","doi-asserted-by":"crossref","first-page":"1285","DOI":"10.1109\/TVLSI.2012.2207748","article-title":"BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture","volume":"21","author":"Atak","year":"2013","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_24","doi-asserted-by":"crossref","unstructured":"Lee, D., Jo, M., Han, K., and Choi, K. (2009, January 9\u201311). FloRA: Coarse-grained reconfigurable architecture with floating-point operation capability. Proceedings of the 2009 International Conference on Field-Programmable Technology, Sydney, NSW, Australia.","DOI":"10.1109\/FPT.2009.5377609"},{"key":"ref_25","doi-asserted-by":"crossref","first-page":"20160893","DOI":"10.1587\/elex.13.20160893","article-title":"Floating-point operation based reconfigurable architecture for radar processing","volume":"13","author":"Feng","year":"2016","journal-title":"IEICE Electron. Express"},{"key":"ref_26","doi-asserted-by":"crossref","unstructured":"Prasad, R., Das, S., Martin, K.J.M., Tagliavini, G., Coussy, P., Benini, L., and Rossi, D. (2020, January 9\u201313). TRANSPIRE: An Energy-Efficient TRANSprecision Floating-Point Programmable ArchItectuRE. Proceedings of the 23rd Conference on Design, Automation and Test in Europe (DATE\u201920), Grenoble, France.","DOI":"10.23919\/DATE48585.2020.9116408"},{"key":"ref_27","doi-asserted-by":"crossref","unstructured":"Wolf, D.L., Jung, L.J., Ruschke, T., Li, C., and Hochberger, C. (2018, January 9\u201311). AMIDAR Project: Lessons Learned in 15 Years of Researching Adaptive Processors. Proceedings of the 2018 13th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), Lille, France.","DOI":"10.1109\/ReCoSoC.2018.8449384"},{"key":"ref_28","doi-asserted-by":"crossref","unstructured":"Dadu, V., Weng, J., Liu, S., and Nowatzki, T. (2019, January 12\u201316). Towards General Purpose Acceleration by Exploiting Common Data-Dependence Forms. Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201952), Columbus, OH, USA.","DOI":"10.1145\/3352460.3358276"},{"key":"ref_29","doi-asserted-by":"crossref","unstructured":"Sato, T. (2005, January 14\u201316). DAPDNA-2 a dynamically reconfigurable processor with 376 32-bit processing elements. Proceedings of the IEEE Hot Chips XVII Symposium (HCS), Stanford, CA, USA.","DOI":"10.1109\/HOTCHIPS.2005.7476596"},{"key":"ref_30","unstructured":"Zhu, M., Liu, L., Yin, S., Wang, Y., Wang, W., and Wei, S. (June, January 30). A reconfigurable multi-processor SoC for media applications. Proceedings of the 2010 IEEE International Symposium on Circuits and Systems, Paris, France."},{"key":"ref_31","doi-asserted-by":"crossref","unstructured":"Das, S., Sivanandan, N., Madhu, K.T., Nandy, S.K., and Narayan, R. (2016, January 4\u20138). RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels. Proceedings of the 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, India.","DOI":"10.1109\/VLSID.2016.29"},{"key":"ref_32","doi-asserted-by":"crossref","unstructured":"Prabhakar, R., Zhang, Y., Koeplinger, D., Feldman, M., Zhao, T., Hadjis, S., Pedram, A., Kozyrakis, C., and Olukotun, K. (2017, January 24\u201328). Plasticine: A reconfigurable architecture for parallel patterns. Proceedings of the 2017 ACM\/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), Toronto, ON, Canada.","DOI":"10.1145\/3079856.3080256"},{"key":"ref_33","doi-asserted-by":"crossref","unstructured":"K\u00e4sgen, P.S., Weinhardt, M., and Hochberger, C. (2018, January 3\u20135). A Coarse-Grained Reconfigurable Array for High-Performance Computing Applications. Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico.","DOI":"10.1109\/RECONFIG.2018.8641720"},{"key":"ref_34","doi-asserted-by":"crossref","unstructured":"Podobas, A., Sano, K., and Matsuoka, S. (2020, January 6\u20138). A Template-based Framework for Exploring Coarse-Grained Reconfigurable Architectures. Proceedings of the 2020 IEEE 31st International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Manchester, UK.","DOI":"10.1109\/ASAP49362.2020.00010"},{"key":"ref_35","unstructured":"De Sousa, J., Martins, V., Lourenco, N., Santos, A., and do Rosario Ribeiro, N. (2012). Reconfigurable Coprocessor Architecture Template for Nested Loops and Programming Tool. (8,276,120), U.S. Patent."},{"key":"ref_36","doi-asserted-by":"crossref","first-page":"385","DOI":"10.1007\/978-3-540-48302-1_42","article-title":"Mapping Applications onto Reconfigurable KressArrays","volume":"Volume 1673","author":"Lysaght","year":"1999","journal-title":"Field Programmable Logic and Applications"},{"key":"ref_37","doi-asserted-by":"crossref","first-page":"126","DOI":"10.1007\/3-540-61730-2_13","article-title":"RaPiD\u2014Reconfigurable Pipelined Datapath","volume":"Volume 1142","author":"Hartenstein","year":"1996","journal-title":"Field-Programmable Logic Smart Applications, New Paradigms and Compilers"},{"key":"ref_38","doi-asserted-by":"crossref","first-page":"167","DOI":"10.1023\/A:1024499601571","article-title":"PACT XPP\u2014A Self-Reconfigurable Data Processing Architecture","volume":"26","author":"Baumgarte","year":"2003","journal-title":"J. Supercomput."},{"key":"ref_39","doi-asserted-by":"crossref","first-page":"1706","DOI":"10.1109\/TMM.2015.2463735","article-title":"An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding","volume":"17","author":"Liu","year":"2015","journal-title":"IEEE Trans. Multimed."},{"key":"ref_40","unstructured":"Santiago, R., de Sousa, J.T., and Lopes, J.D. (2017, January 30\u201331). Compiler for the Versat Architecture. Proceedings of the XIII Jornadas de Sistemas Reconfigur\u00e1veis, Aveiro, Portugal."},{"key":"ref_41","doi-asserted-by":"crossref","first-page":"788","DOI":"10.1016\/j.micpro.2014.05.009","article-title":"Parallel Distributed Scalable Runtime Address Generation Scheme for a Coarse Grain Reconfigurable Computation and Storage Fabric","volume":"38","author":"Farahini","year":"2014","journal-title":"Microprocess. Microsyst."},{"key":"ref_42","doi-asserted-by":"crossref","unstructured":"Liu, D., Yin, S., Liu, L., and Wei, S. (June, January 29). Polyhedral model based mapping optimization of loop nests for CGRAs. Proceedings of the 2013 50th ACM\/EDAC\/IEEE Design Automation Conference (DAC), Austin, TX, USA.","DOI":"10.1145\/2463209.2488757"},{"key":"ref_43","unstructured":"Lopes, J.D., and de Sousa, J.T. (2017, January 19\u201322). Fast Fourier Transform on the Versat CGRA. Proceedings of the Jornadas Sarteco, Malaga, Spain."},{"key":"ref_44","doi-asserted-by":"crossref","unstructured":"Lopes, J.D., de Sousa, J.T., and Neto, H. (2017, January 4\u20138). K-Means Clustering on CGRA. Proceedings of the 27th International Conference on Field-Programmable Logic and Applications, New Paradigms and Compilers (FPL 2017), Ghent, Belgium.","DOI":"10.23919\/FPL.2017.8056854"},{"key":"ref_45","unstructured":"Wang, W., and Dey, T. (2016, April 16). A Survey on ARM Cortex A Processors. Available online: http:\/\/www.cs.virginia.edu\/skadron\/cs8535s11\/armcortex.pdf."},{"key":"ref_46","doi-asserted-by":"crossref","first-page":"23","DOI":"10.1109\/40.782564","article-title":"Design challenges of technology scaling","volume":"19","author":"Borkar","year":"1999","journal-title":"IEEE Micro"},{"key":"ref_47","unstructured":"Kamalizad, A.H., Pan, C., and Bagherzadeh, N. (2003, January 12). Fast parallel FFT on a reconfigurable computation platform. Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing, Sao Paulo, Brazil."}],"container-title":["Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2079-9292\/10\/6\/669\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T05:34:48Z","timestamp":1760160888000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2079-9292\/10\/6\/669"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,3,12]]},"references-count":47,"journal-issue":{"issue":"6","published-online":{"date-parts":[[2021,3]]}},"alternative-id":["electronics10060669"],"URL":"https:\/\/doi.org\/10.3390\/electronics10060669","relation":{},"ISSN":["2079-9292"],"issn-type":[{"value":"2079-9292","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,3,12]]}}}