{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T02:18:48Z","timestamp":1760235528263,"version":"build-2065373602"},"reference-count":11,"publisher":"MDPI AG","issue":"17","license":[{"start":{"date-parts":[[2021,8,27]],"date-time":"2021-08-27T00:00:00Z","timestamp":1630022400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100001871","name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","doi-asserted-by":"publisher","award":["UIDB\/00319\/2020"],"award-info":[{"award-number":["UIDB\/00319\/2020"]}],"id":[{"id":"10.13039\/501100001871","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Electronics"],"abstract":"<jats:p>To address the integration of software threads and hardware accelerators into the Linux Operating System (OS) programming models, an accelerator architecture is proposed, based on micro-programmable hardware system calls, which fully export these resources into the Linux OS user-space through a design-specific virtual file system. The proposed HAL-ASOS accelerator model is split into a user-defined Hardware Task and a parameterizable Hardware Kernel with three differentiated transfer channels, aiming to explore distinct BUS technology interfaces and promote the accelerator to a first-class computing unit. This paper focuses on the Hardware Kernel and mainly its microcode control unit, which will leverage the elasticity to naturally evolve with Linux OS through key differentiating capabilities of field programmable gate arrays (FPGAs) when compared to the state of the art. To comply with the evolutive nature of Linux OS, or any Hardware Task incremental features, the proposed model generates page-faults signaling runtime errors that are handled at the kernel level as part of the virtual file system runtime. To evaluate the accelerator model\u2019s programmability and its performance, a client-side application based on the AES 128-bit algorithm was implemented. Experiments demonstrate a flexible design approach in terms of hardware and software reconfiguration and significant performance increases consistent with rising processing demands or clock design frequencies.<\/jats:p>","DOI":"10.3390\/electronics10172078","type":"journal-article","created":{"date-parts":[[2021,8,27]],"date-time":"2021-08-27T09:53:23Z","timestamp":1630058003000},"page":"2078","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["HAL-ASOS Accelerator Model: Evolutive Elasticity by Design"],"prefix":"10.3390","volume":"10","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9006-6139","authenticated-orcid":false,"given":"V\u00edtor","family":"Silva","sequence":"first","affiliation":[{"name":"ALGORITMI Centre, University of Minho, 4800-058 Guimar\u00e3es, Portugal"}]},{"given":"Paulo","family":"Pinto","sequence":"additional","affiliation":[{"name":"ALGORITMI Centre, University of Minho, 4800-058 Guimar\u00e3es, Portugal"}]},{"given":"Paulo","family":"Cardoso","sequence":"additional","affiliation":[{"name":"ALGORITMI Centre, University of Minho, 4800-058 Guimar\u00e3es, Portugal"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9954-9746","authenticated-orcid":false,"given":"Jorge","family":"Cabral","sequence":"additional","affiliation":[{"name":"ALGORITMI Centre, University of Minho, 4800-058 Guimar\u00e3es, Portugal"},{"name":"CEIIA Centro de Engenharia e Desenvolvimento de Produto, 4550-017 Matosinhos, Portugal"}]},{"given":"Adriano","family":"Tavares","sequence":"additional","affiliation":[{"name":"ALGORITMI Centre, University of Minho, 4800-058 Guimar\u00e3es, Portugal"}]}],"member":"1968","published-online":{"date-parts":[[2021,8,27]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"148975","DOI":"10.1109\/ACCESS.2019.2943179","article-title":"A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing","volume":"7","author":"Zhu","year":"2019","journal-title":"IEEE Open Access J."},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"60","DOI":"10.1109\/MM.2013.110","article-title":"ReconOS\u2014An Operating System Approach for Reconfigurable Computing","volume":"34","author":"Agne","year":"2014","journal-title":"IEEE Micro"},{"key":"ref_3","doi-asserted-by":"crossref","unstructured":"Ordaz-Garc\u00eda, O.O., Ortiz-L\u00f3pez, M., Quiles-Latorre, F.J., Arceo-Olague, J.G., Sol\u00eds-Robles, R., and Bellido-Outeiri\u00f1o, F.J. (2020). DALI Bridge FPGA-Based Implementation in a Wireless Sensor Node for IoT Street Lighting Applications. Electronics, 9.","DOI":"10.3390\/electronics9111803"},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1109\/MM.2004.36","article-title":"Programming models for hybrid FPGA-CPU computational components: A missing link","volume":"24","author":"Andrews","year":"2004","journal-title":"IEEE Micro"},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"198","DOI":"10.1016\/j.micpro.2018.05.017","article-title":"Using dynamic partial reconfiguration of FPGAs in real-Time systems","volume":"61","author":"Pezzarossa","year":"2018","journal-title":"Microprocess. Microsyst."},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"180","DOI":"10.1016\/j.vlsi.2020.11.011","article-title":"Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing","volume":"77","author":"Vu","year":"2021","journal-title":"Integration"},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3405794","article-title":"FOS: A Modular FPGA Operating System for Dynamic Workloads","volume":"13","author":"Vaishnav","year":"2020","journal-title":"ACM Trans. Reconfig. Technol. Syst."},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"092102","DOI":"10.1007\/s11432-017-9418-9","article-title":"Building application-specific operating systems: A profile-guided approach","volume":"61","author":"Yuan","year":"2018","journal-title":"Sci. China Inf. Sci."},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"Kollenda, B., Koppe, P., Fyrbiak, M., Kison, C., Paar, C., and Holz, T. (2018, January 15\u201319). An Exploratory Analysis of Microcode as a Building Block for System Defenses. Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, Toronto, ON, Canada.","DOI":"10.1145\/3243734.3243861"},{"key":"ref_10","unstructured":"Sharifi, R., and Venkat, A. (June, January 30). CHEx86: Context-Sensitive Enforcement of Memory Safety via Microcode-Enabled Capabilities. Proceedings of the ACM\/IEEE 47th Annual International Symposium on Computer Architecture, Valencia, Spain."},{"key":"ref_11","doi-asserted-by":"crossref","unstructured":"Skarlatos, D., Chen, Q., Chen, J., Xu, T., and Torrellas, J. (2020, January 17\u201321). Draco: Architectural and Operating System Support for System Call Security. Proceedings of the 53rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), Athens, Greece.","DOI":"10.1109\/MICRO50266.2020.00017"}],"container-title":["Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2079-9292\/10\/17\/2078\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T06:53:32Z","timestamp":1760165612000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2079-9292\/10\/17\/2078"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,8,27]]},"references-count":11,"journal-issue":{"issue":"17","published-online":{"date-parts":[[2021,9]]}},"alternative-id":["electronics10172078"],"URL":"https:\/\/doi.org\/10.3390\/electronics10172078","relation":{},"ISSN":["2079-9292"],"issn-type":[{"type":"electronic","value":"2079-9292"}],"subject":[],"published":{"date-parts":[[2021,8,27]]}}}