{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T04:48:36Z","timestamp":1760244516661,"version":"build-2065373602"},"reference-count":25,"publisher":"MDPI AG","issue":"1","license":[{"start":{"date-parts":[[2022,12,27]],"date-time":"2022-12-27T00:00:00Z","timestamp":1672099200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100001871","name":"FCT\/MCTES","doi-asserted-by":"publisher","award":["UIDB\/50008\/2020","FCT-SFRH\/BD\/07123\/2021"],"award-info":[{"award-number":["UIDB\/50008\/2020","FCT-SFRH\/BD\/07123\/2021"]}],"id":[{"id":"10.13039\/501100001871","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Electronics"],"abstract":"<jats:p>Analog IC design is characterized by non-systematic re-design iterations, often requiring partial or complete layout re-design. The layout task usually starts with device placement, where the several performance figures and constraints to be met escalate its complexity immensely, and, due to the inherent tradeoffs, an \u201coptimal\u201d floorplan solution does not usually exist. Deep learning models are now establishing for the automation of the placement task of analog integrated circuit layout design, promising to bypass the limitations of existing approaches based on: time-consuming optimization processes with several constraints; or placement retargeting from legacy designs\/templates, which rely heavily on legacy layout data. However, as the complexity of analog design cases tackled by these methodologies increases, a broader set of topological constraints must be supported to cover the different layout styles and circuit classes. Here, model-independent differentiable encodings for regularity, boundary, proximity, and symmetry island constraints are formulated for the first time in the literature, and an unsupervised loss function is used for the artificial neural network model to learn how to generate placements that follow them. The use of a deep learning model makes push-button speed placement generation possible, additionally, as only sizing data are required for its training, it discards the need to acquire legacy layouts containing insights into this vast set of, often neglected, constraints. The model is ultimately used to produce floorplans from scratch at push-button speed for real state-of-the-art analog structures, including technology nodes not used for training. A case-study comparison with a floorplan design made by a human-expert presents improvements in the fulfillment of every constraint, reaching an overall improvement of around 70%, demonstrating the approach\u2019s value in placement design.<\/jats:p>","DOI":"10.3390\/electronics12010110","type":"journal-article","created":{"date-parts":[[2022,12,28]],"date-time":"2022-12-28T05:28:24Z","timestamp":1672205304000},"page":"110","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Differentiable Constraints\u2019 Encoding for Gradient-Based Analog Integrated Circuit Placement Optimization"],"prefix":"10.3390","volume":"12","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7362-2407","authenticated-orcid":false,"given":"Ant\u00f3nio","family":"Gusm\u00e3o","sequence":"first","affiliation":[{"name":"Instituto de Telecomunica\u00e7\u00f5es, Universidade de Lisboa, 1049-001 Lisboa, Portugal"},{"name":"Instituto Superior T\u00e9cnico, Universidade de Lisboa, 1049-001 Lisboa, Portugal"}]},{"given":"Pedro","family":"Alves","sequence":"additional","affiliation":[{"name":"Instituto de Telecomunica\u00e7\u00f5es, Universidade de Lisboa, 1049-001 Lisboa, Portugal"},{"name":"Instituto Superior T\u00e9cnico, Universidade de Lisboa, 1049-001 Lisboa, Portugal"}]},{"given":"Nuno","family":"Horta","sequence":"additional","affiliation":[{"name":"Instituto de Telecomunica\u00e7\u00f5es, Universidade de Lisboa, 1049-001 Lisboa, Portugal"},{"name":"Instituto Superior T\u00e9cnico, Universidade de Lisboa, 1049-001 Lisboa, Portugal"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9625-6435","authenticated-orcid":false,"given":"Nuno","family":"Louren\u00e7o","sequence":"additional","affiliation":[{"name":"Instituto de Telecomunica\u00e7\u00f5es, Universidade de Lisboa, 1049-001 Lisboa, Portugal"},{"name":"Departamento de Inform\u00e1tica, Universidade de \u00c9vora, 7005-869 \u00c9vora, Portugal"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8251-1415","authenticated-orcid":false,"given":"Ricardo","family":"Martins","sequence":"additional","affiliation":[{"name":"Instituto de Telecomunica\u00e7\u00f5es, Universidade de Lisboa, 1049-001 Lisboa, Portugal"},{"name":"Instituto Superior T\u00e9cnico, Universidade de Lisboa, 1049-001 Lisboa, Portugal"}]}],"member":"1968","published-online":{"date-parts":[[2022,12,27]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"791","DOI":"10.1109\/TCAD.2009.2017433","article-title":"Analog Placement Based on Symmetry-Island Formulation","volume":"28","author":"Lin","year":"2009","journal-title":"IEEE Trans. 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