{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T15:46:59Z","timestamp":1774367219721,"version":"3.50.1"},"reference-count":43,"publisher":"MDPI AG","issue":"4","license":[{"start":{"date-parts":[[2023,2,6]],"date-time":"2023-02-06T00:00:00Z","timestamp":1675641600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"VALORIZA\u2014Research Center for Endogenous Resource Valorization","award":["UIDB\/05064\/2020"],"award-info":[{"award-number":["UIDB\/05064\/2020"]}]},{"name":"VALORIZA\u2014Research Center for Endogenous Resource Valorization","award":["UIDB\/04111\/2020"],"award-info":[{"award-number":["UIDB\/04111\/2020"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Electronics"],"abstract":"<jats:p>The increasing complexity of System-on-Chip (SoC) and the ongoing technology miniaturization on Integrated Circuit (IC) manufacturing processes makes modern SoCs more susceptible to Single-Event Effects (SEE) caused by radiation, even at sea level. To provide realistic estimates at a low cost, efficient analysis techniques capable of replicating SEEs are required. Among these methods, fault injection through emulation using Field-Programmable Gate Array (FPGA) enables campaigns to be run on a Circuit Under Test (CUT). This paper investigates the use of an FPGA architecture to speed up the execution of fault campaigns. As a result, a new methodology for mapping the CUT occupation on the FPGA is proposed, significantly reducing the total number of faults to be injected. In addition, a fault injection technique\/flow is proposed to demonstrate the benefits of cutting-edge approaches. The presented technique emulates Single-Event Transient (SET) in all combinatorial elements of the CUT using the Internal Configuration Access Port (ICAP) of Xilinx FPGAs.<\/jats:p>","DOI":"10.3390\/electronics12040807","type":"journal-article","created":{"date-parts":[[2023,2,6]],"date-time":"2023-02-06T05:29:05Z","timestamp":1675661345000},"page":"807","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":11,"title":["A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP"],"prefix":"10.3390","volume":"12","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9550-1822","authenticated-orcid":false,"given":"Frederico","family":"Ferlini","sequence":"first","affiliation":[{"name":"System & Verification Group, Cadence Design Systems GmbH, 85622 Feldkirchen, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0972-2160","authenticated-orcid":false,"given":"Felipe","family":"Viel","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Federal University of Santa Catarina (UFSC), Florian\u00f3polis 88040-900, Brazil"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6806-9122","authenticated-orcid":false,"given":"Laio Oriel","family":"Seman","sequence":"additional","affiliation":[{"name":"Graduate Program in Applied Computer Science, University of Vale do Itaja\u00ed (UNIVALI), Itaja\u00ed 88302-901, Brazil"}]},{"given":"Hector","family":"Pettenghi","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Federal University of Santa Catarina (UFSC), Florian\u00f3polis 88040-900, Brazil"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2191-6064","authenticated-orcid":false,"given":"Eduardo Augusto","family":"Bezerra","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Federal University of Santa Catarina (UFSC), Florian\u00f3polis 88040-900, Brazil"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0446-9271","authenticated-orcid":false,"given":"Valderi Reis Quietinho","family":"Leithardt","sequence":"additional","affiliation":[{"name":"COPELABS\u2014Lus\u00f3fona University of Humanities and Technologies, Campo Grande 376, 1749-024 Lisboa, Portugal"},{"name":"VALORIZA, Research Center for Endogenous Resources Valorization, Instituto Polit\u00e9cnico de Portalegre, 7300-555 Portalegre, Portugal"}]}],"member":"1968","published-online":{"date-parts":[[2023,2,6]]},"reference":[{"key":"ref_1","unstructured":"Makowski, D. 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