{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,31]],"date-time":"2025-12-31T14:30:35Z","timestamp":1767191435483,"version":"3.48.0"},"reference-count":23,"publisher":"MDPI AG","issue":"1","license":[{"start":{"date-parts":[[2025,12,30]],"date-time":"2025-12-30T00:00:00Z","timestamp":1767052800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Electronics"],"abstract":"<jats:p>This paper presents an FPGA-based architecture for real-time spline-based signal reconstruction, targeted at multimedia signal processing applications. Leveraging the multi-resolution properties of B-splines, the proposed design enables efficient upsampling, denoising, and feature preservation for image and video signals. Implemented on a mid-range FPGA, the system supports parallel processing of multiple channels, with low-latency memory access and pipelined arithmetic units. The proposed pipeline achieves a throughput of up to 33.1 megasmples per second for 1D signals and 19.4 megapixels per second for 2D images, while maintaining average power consumption below 250 mW. Compared to CPU and embedded GPU implementations, the design delivers &gt;15\u00d7 improvement in energy efficiency and deterministic low-latency performance (8\u201312 clock cycles). A key novelty lies in combining multi-resolution B-spline reconstruction with fixed-point arithmetic and streaming-friendly pipelining, making the architecture modular, compact, and robust to varying input rates. Benchmarking results on synthetic and real multimedia datasets show significant improvements in throughput and energy efficiency compared to conventional CPU and GPU implementations. The architecture supports flexible resolution scaling, making it suitable for edge-computing scenarios in multimedia environments.<\/jats:p>","DOI":"10.3390\/electronics15010173","type":"journal-article","created":{"date-parts":[[2025,12,31]],"date-time":"2025-12-31T14:08:11Z","timestamp":1767190091000},"page":"173","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["FPGA-Accelerated Multi-Resolution Spline Reconstruction for Real-Time Multimedia Signal Processing"],"prefix":"10.3390","volume":"15","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8872-5721","authenticated-orcid":false,"given":"Manuel J. C. S.","family":"Reis","sequence":"first","affiliation":[{"name":"Engineering Departement\/IEETA, University of Tr\u00e1s-os-Montes e Alto Douro, Quinta de Prados, 5000-801 Vila Real, Portugal"}]}],"member":"1968","published-online":{"date-parts":[[2025,12,30]]},"reference":[{"key":"ref_1","first-page":"2610","article-title":"Generalized Sampling: Stability and Performance Analysis","volume":"53","author":"Unser","year":"2005","journal-title":"IEEE Trans. Signal Process."},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"532","DOI":"10.1109\/TCOM.1983.1095851","article-title":"The Laplacian Pyramid as a Compact Image Code","volume":"31","author":"Burt","year":"1983","journal-title":"IEEE Trans. Commun."},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"22","DOI":"10.1109\/79.799930","article-title":"Splines: A perfect fit for signal and image processing","volume":"16","author":"Unser","year":"1999","journal-title":"IEEE Signal Process. Mag."},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"4014","DOI":"10.35940\/ijrte.D8351.118419","article-title":"VLSI Architecture of Cubic Spline Interpolation on FPGA","volume":"8","author":"Jayakumar","year":"2019","journal-title":"Int. J. Recent Technol. Eng. (IJRTE)"},{"key":"ref_5","doi-asserted-by":"crossref","unstructured":"Popovic, V., Seyid, K., Schmid, A., and Leblebici, Y. (2013, January 26\u201331). Real-time hardware implementation of multi-resolution image blending. Proceedings of the 2013 IEEE International Conference on Acoustics, Speech and Signal Processing, Vancouver, BC, Canada.","DOI":"10.1109\/ICASSP.2013.6638155"},{"key":"ref_6","doi-asserted-by":"crossref","unstructured":"Kryjak, T. (2024, January 28\u201330). Event-Based Vision on FPGAs\u2014A Survey. Proceedings of the 2024 27th Euromicro Conference on Digital System Design (DSD), Paris, France.","DOI":"10.1109\/DSD64264.2024.00078"},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Guo, L., and Wu, S. (2023). FPGA Implementation of a Real-Time Edge Detection System Based on an Improved Canny Algorithm. Appl. Sci., 13.","DOI":"10.3390\/app13020870"},{"key":"ref_8","doi-asserted-by":"crossref","unstructured":"Hashimoto, N., and Takamaeda-Yamazaki, S. (September, January 30). An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising. Proceedings of the 2021 31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany.","DOI":"10.1109\/FPL53798.2021.00035"},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"Liu, J., Zhou, X., Wan, Z., Yang, X., He, W., He, R., and Lin, Y. (2023). Multi-Scale FPGA-Based Infrared Image Enhancement by Using RGF and CLAHE. Sensors, 23.","DOI":"10.3390\/s23198101"},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"901","DOI":"10.1007\/s11554-020-01035-1","article-title":"FPGA-based architecture for bi-cubic interpolation: The best trade-off between precision and hardware resource consumption","volume":"18","author":"Boukhtache","year":"2021","journal-title":"J. Real-Time Image Process."},{"key":"ref_11","doi-asserted-by":"crossref","unstructured":"Jiang, Y., Vaicaitis, A., Dooley, J., and Leeser, M. (2024). Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function. Sensors, 24.","DOI":"10.20944\/preprints202401.1463.v1"},{"key":"ref_12","doi-asserted-by":"crossref","first-page":"105431","DOI":"10.1016\/j.cmpb.2020.105431","article-title":"Accelerating B-spline Interpolation on GPUs: Application to Medical Image Registration","volume":"193","author":"Zachariadis","year":"2020","journal-title":"Comput. Methods Programs Biomed."},{"key":"ref_13","doi-asserted-by":"crossref","unstructured":"Ahmadi, M., Vakili, S., and Langlois, J.M.P. (2020, January 16\u201319). An Energy-Efficient Accelerator Architecture with Serial Accumulation Dataflow for Deep CNNs. Proceedings of the 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS), Montreal, QC, Canada.","DOI":"10.1109\/NEWCAS49341.2020.9159818"},{"key":"ref_14","doi-asserted-by":"crossref","unstructured":"Perez-Portero, A., Querol, J., and Camps, A. (2024). Resource-Efficient FPGA Architecture for Real-Time RFI Mitigation in Interferometric Radiometers. Sensors, 24.","DOI":"10.3390\/s24248001"},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"183","DOI":"10.5201\/ipol.2019.257","article-title":"Optimization of Image B-spline Interpolation for GPU Architectures","volume":"9","author":"Briand","year":"2019","journal-title":"Image Process. Line"},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"1439","DOI":"10.1109\/TSP.2005.843699","article-title":"Cardinal exponential splines: Part II-think analog, act digital","volume":"53","author":"Unser","year":"2005","journal-title":"IEEE Trans. Signal Process."},{"key":"ref_17","doi-asserted-by":"crossref","first-page":"1425","DOI":"10.1109\/TSP.2005.843700","article-title":"Cardinal exponential splines: Part I-theory and filtering algorithms","volume":"53","author":"Unser","year":"2005","journal-title":"IEEE Trans. Signal Process."},{"key":"ref_18","doi-asserted-by":"crossref","unstructured":"de Boor, C. (1978). A Practical Guide to Splines, Springer. Applied Mathematical Sciences.","DOI":"10.1007\/978-1-4612-6333-3"},{"key":"ref_19","doi-asserted-by":"crossref","first-page":"821","DOI":"10.1109\/78.193220","article-title":"B-spline signal processing. I. Theory","volume":"41","author":"Unser","year":"1993","journal-title":"IEEE Trans. Signal Process."},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"154","DOI":"10.1109\/12.565590","article-title":"Design issues in division and other floating-point operations","volume":"46","author":"Oberman","year":"1997","journal-title":"IEEE Trans. Comput."},{"key":"ref_21","unstructured":"Xilinx, Inc. (2025, June 11). DSP48E1 Slice User Guide. Available online: https:\/\/docs.amd.com\/v\/u\/en-US\/ug479_7Series_DSP48E1\/."},{"key":"ref_22","unstructured":"Xilinx, Inc. (2025, June 11). Vivado Design Suite User Guide. Available online: https:\/\/www.xilinx.com\/products\/design-tools\/vivado.html."},{"key":"ref_23","unstructured":"Siemens EDA (Formerly Mentor Graphics) (2025, June 11). ModelSim Simulation and Debugging. Available online: https:\/\/eda.sw.siemens.com\/en-US\/products\/ic\/modelsim\/."}],"container-title":["Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2079-9292\/15\/1\/173\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,31]],"date-time":"2025-12-31T14:26:12Z","timestamp":1767191172000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2079-9292\/15\/1\/173"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,12,30]]},"references-count":23,"journal-issue":{"issue":"1","published-online":{"date-parts":[[2026,1]]}},"alternative-id":["electronics15010173"],"URL":"https:\/\/doi.org\/10.3390\/electronics15010173","relation":{},"ISSN":["2079-9292"],"issn-type":[{"value":"2079-9292","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,12,30]]}}}