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An algorithm is applied to reduce and adjust the order of the filter in linear equalizer according to the channel conditions. The proposed design is implemented in the synopsis TSMC 65nm technology. The results from using the algorithm uses 28% less power when compared with the conventional 64-tap fixed length adaptive filter design. It has also been shown that the low-complexity of the additional circuitry needed for the variable length adaptive filter presents minimal overhead for this architecture.<\/p>","DOI":"10.4018\/ijec.2020100105","type":"journal-article","created":{"date-parts":[[2020,8,26]],"date-time":"2020-08-26T13:50:13Z","timestamp":1598449813000},"page":"59-71","source":"Crossref","is-referenced-by-count":7,"title":["ASIC Implementation of Linear Equalizer Using Adaptive FIR Filter"],"prefix":"10.4018","volume":"16","author":[{"family":"Grande Naga Jyothi","sequence":"first","affiliation":[{"name":"Vellore Institute of Technology, India"}]},{"given":"Anusha","family":"Gorantla","sequence":"additional","affiliation":[{"name":"Qis College of Engineering and Technology, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1951-1188","authenticated-orcid":true,"given":"Thirumalesu","family":"Kudithi","sequence":"additional","affiliation":[{"name":"Vellore Institute of Technology, India"}]}],"member":"2432","reference":[{"key":"IJeC.2020100105-0","first-page":"IV","article-title":"Low power implementation of high throughput FIR filters. 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