{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,10]],"date-time":"2026-06-10T16:00:06Z","timestamp":1781107206452,"version":"3.54.1"},"reference-count":32,"publisher":"IGI Global Scientific Publishing","issue":"1","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,1,1]]},"abstract":"<p>OpenSPARC is the only 64-bit Chip Multi-Threaded (CMT) processor that has ever been made open-source and non-proprietary. In this paper, the authors present an FPGA-based embedded system and methodology for prototyping and validating the OpenSPARC processor. They also present synthesis and performance evaluation results for OpenSPARC on a Virtex-5 FPGA platform. Light version of OpenSolaris was successfully booted on the platform, and the High Performance Embedded Computing (HPEC) benchmark suite was used to evaluate the performance. Xilinx ISE suite was used for synthesis, implementation, and chip programming. The down-scaled FPGA implementation of the processor runs at 81.3 MHz. The whole processor would require about 176453 Virtex-5 logic slices. To the best of their knowledge, they are the first researchers to report detailed FPGA synthesis results for OpenSPARC and evaluate its performance on FPGA using the HPEC benchmarks. Other researchers may find these results useful when comparing with other processors or studying the impact of a certain design change or addition on performance and cost.<\/p>","DOI":"10.4018\/ijertcs.2014010104","type":"journal-article","created":{"date-parts":[[2014,12,10]],"date-time":"2014-12-10T07:21:02Z","timestamp":1418196062000},"page":"61-74","source":"Crossref","is-referenced-by-count":0,"title":["OpenSPARC Processor Evaluation Using Virtex-5 FPGA and High Performance Embedded Computing (HPEC) Benchmark Suite"],"prefix":"10.4018","volume":"5","author":[{"given":"Khaldoon Moosa","family":"Mhaidat","sequence":"first","affiliation":[{"name":"Jordan University of Science and Technology, Irbid, Jordan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ahmad","family":"Baset","sequence":"additional","affiliation":[{"name":"Jordan University of Science and Technology, Irbid, Jordan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Osama","family":"Al-Khaleel","sequence":"additional","affiliation":[{"name":"Jordan University of Science and Technology, Irbid, Jordan"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"2432","reference":[{"key":"ijertcs.2014010104-0","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2012.05.015"},{"key":"ijertcs.2014010104-1","unstructured":"ARM. (2013, December). How FPGA boards help to validate ARM processors. Retrieved December 13, 2013, from http:\/\/community.arm.com\/groups\/tools\/blog\/2013\/12\/03\/how-fpga-boards-help-to-validate-arm-processors"},{"key":"ijertcs.2014010104-2","unstructured":"BEEcube. (2013). BEE4 All programmable rack servers. Retrieved November 5, 2013, from http:\/\/www.beecube.com\/products\/BEE4.asp"},{"key":"ijertcs.2014010104-3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168949"},{"key":"ijertcs.2014010104-4","unstructured":"Bluespec. (2012). Bluespec SystemVerilog reference guide. Retrieved October 26, 2013, from http:\/\/www.bluespec.com\/forum\/download.php?id=157"},{"key":"ijertcs.2014010104-5","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2009.5185385"},{"key":"ijertcs.2014010104-6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2057870"},{"key":"ijertcs.2014010104-7","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344684"},{"key":"ijertcs.2014010104-8","doi-asserted-by":"crossref","unstructured":"Chung, E. S., Papamichael, M., Nurvitadhi, E., Hoe, J. C., Mai, K., & Falsafi, B. (2009). ProtoFlex: Towards scalable, full-system multiprocessor simulations using FPGAs. ACM Transactions on Reconfigurable Technology and Systems, 2(2).","DOI":"10.1145\/1534916.1534925"},{"key":"ijertcs.2014010104-9","unstructured":"Davis, J. D., Thacker, C., & Chang, C. (2009). BEE3: Revitalizing computer architecture research (Microsoft Research, Tech. Rep. MSR-TR-2009-45). Microsoft."},{"key":"ijertcs.2014010104-10","doi-asserted-by":"crossref","unstructured":"Govindaraju, V., Ho, C.-H., & Sankaralingam, K. (2012). Dynamically specialized datapaths for energy efficient computing. In Proceedings of the17th IEEE International Symposium on High Performance Computer Architecture. IEEE.","DOI":"10.1109\/HPCA.2011.5749755"},{"key":"ijertcs.2014010104-11","doi-asserted-by":"crossref","unstructured":"Grohoski, G., Barreh, J., Brooks, J., Golla, R., Grohoski, G., Hetherington, R., et al. (2006). Niagara-2: A highly threaded server-on-a-chip. In Proceedings of the18th Hot Chips Symposium. Academic Press.","DOI":"10.1109\/HOTCHIPS.2006.7477874"},{"key":"ijertcs.2014010104-12","doi-asserted-by":"crossref","unstructured":"Horowitz, M., & Dally, W. (2004). How scaling will change processor architecture. In Proceedings of theIEEE International Solid-State Circuits Conference (ISSCC). IEEE.","DOI":"10.1109\/ISSCC.2004.1332629"},{"key":"ijertcs.2014010104-13","doi-asserted-by":"crossref","unstructured":"Leon, A., Langley, B., & Shin, J. (2006). The UltraSPARCTM T1 processor: CMT reliability. In Proceedings of theIEEE Custom Integrated Circuits Conference. IEEE.","DOI":"10.1109\/CICC.2006.320989"},{"key":"ijertcs.2014010104-14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.885049"},{"key":"ijertcs.2014010104-15","unstructured":"Massachusetts Institute of Technology. (2013). HPEC challenge benchmark suite. Retrieved June 27, 2013, from http:\/\/www.ll.mit.edu\/HPECchallenge"},{"key":"ijertcs.2014010104-16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373611"},{"key":"ijertcs.2014010104-17","unstructured":"OpenCores. (2013). Plasma soft core. Retrieved October 25, 2013, from http:\/\/opencores.org\/project,plasma"},{"key":"ijertcs.2014010104-18","unstructured":"Oracle. (2013, July). Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture. Retrieved January 15, 2014, from http:\/\/www.oracle.com\/technetwork\/server-storage\/sun-sparc-enterprise\/documentation\/o13-024-sparc-t5-architecture-1920540.pdf"},{"key":"ijertcs.2014010104-19","unstructured":"Oracle. (2013, September). SPARC M6-32 server architecture. Retrieved January 15, 2014, from http:\/\/www.oracle.com\/technetwork\/server-storage\/sun-sparc-enterprise\/documentation\/o13-066-sparc-m6-32-architecture-2016053.pdf?ssSourceSiteId=ocomen"},{"key":"ijertcs.2014010104-20","unstructured":"Parulkar, I., Wood, A., Hoe, J. C., Falsafi, B., Adve, S. V., & Torrellas, J. (2008). OpenSPARC: An open platform for hardware reliability experimentation. In Proceedings of the 4th Workshop on Silicon Errors in Logic-System Effects (SELSE). SELSE."},{"key":"ijertcs.2014010104-21","unstructured":"Princeton University. (2013). PALMS OpenSPARC security and performance research platform. Retrieved August 18, 2013, from http:\/\/palms.ee.princeton.edu\/opensparc"},{"key":"ijertcs.2014010104-22","doi-asserted-by":"crossref","unstructured":"Shah, M., Barren, J., Brooks, J., Golla, R., Grohoski, G., Gura, N., et al. (2007). UltraSPARCTM T2: A highly-threaded, power-efficient, SPARC SOC. In Proceedings of theIEEE Asian Solid-State Circuits Conference (ASSCC). IEEE.","DOI":"10.1109\/ASSCC.2007.4425786"},{"key":"ijertcs.2014010104-23","year":"2009","journal-title":"OpenSPARC T1 processor design and verification user\u2019s guide"},{"key":"ijertcs.2014010104-24","unstructured":"Synopsys. (2013, December). Modern FPGA-based prototyping systems accelerate the transition from stand-alone IP block validation to integrated systems. Retrieved December 13, 2013, from http:\/\/www.synopsys.com\/Company\/Publications\/DWTB\/Pages\/dwtb-fpga-2013Q3.aspx"},{"key":"ijertcs.2014010104-25","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2011.5929973"},{"key":"ijertcs.2014010104-26","unstructured":"Thatcher, T., & Hartke, P. (2008, August). OpenSPARC T1 on Xilinx FPGAs \u2013 Updates. RAMP Retreat."},{"key":"ijertcs.2014010104-27","author":"D.Weaver","year":"2008","journal-title":"OpenSPARC internals"},{"key":"ijertcs.2014010104-28","author":"R.Wiley","year":"2011","journal-title":"Performance variability analysis of the OpenSPARC architecture on FPGAs (tech report)."},{"key":"ijertcs.2014010104-29","unstructured":"Xilinx. (2011, March). MicroBlaze processor reference guide. Retrieved May 16, 2013, from http:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx13_1\/mb_ref_guide.pdf"},{"key":"ijertcs.2014010104-30","unstructured":"Xilinx. (2012). Virtex-5 FPGA user guide. Retrieved May 4, 2013, from http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug190.pdf"},{"key":"ijertcs.2014010104-31","unstructured":"Xilinx. (2013). Xilinx university program XUPV5-LX110T development system. Retrieved May 4, 2013, from http:\/\/www.xilinx.com\/univ\/xupv5-lx110t.htm"}],"container-title":["International Journal of Embedded and Real-Time Communication Systems"],"original-title":[],"language":"ng","link":[{"URL":"https:\/\/www.igi-global.com\/viewtitle.aspx?TitleId=120316","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T16:34:13Z","timestamp":1654101253000},"score":1,"resource":{"primary":{"URL":"https:\/\/services.igi-global.com\/resolvedoi\/resolve.aspx?doi=10.4018\/ijertcs.2014010104"}},"subtitle":[""],"short-title":[],"issued":{"date-parts":[[2014,1,1]]},"references-count":32,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2014,1]]}},"URL":"https:\/\/doi.org\/10.4018\/ijertcs.2014010104","relation":{},"ISSN":["1947-3176","1947-3184"],"issn-type":[{"value":"1947-3176","type":"print"},{"value":"1947-3184","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,1,1]]}}}