{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T16:14:58Z","timestamp":1654100098067},"reference-count":23,"publisher":"IGI Global","issue":"2","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,7,1]]},"abstract":"<p>FPGAs have been used as a target platform because they have increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercially affordable. These trends make FPGAs an alternative in application areas where extensive data processing plays an important role. Consequently, the desire emerges for early performance estimation in order to quantify the FPGA approach. A mathematical model has been presented that estimates the maximum number of LUTs consumed by the hardware synthesized for different FPGAs using LLVM.. The motivation behind this research work is to design an area modeling approach for FPGA based implementation at an early stage of design. The equation based area estimation model permits immediate and accurate estimation of resources. Two important criteria used to judge the quality of the results were estimation accuracy and runtime. Experimental results show that estimation error is in the range of 1.33% to 7.26% for Spartan 3E, 1.6% to 5.63% for Virtex-2pro and  2.3% to 6.02% for Virtex-5.<\/p>","DOI":"10.4018\/ijertcs.2016070103","type":"journal-article","created":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T13:42:00Z","timestamp":1490362920000},"page":"35-44","source":"Crossref","is-referenced-by-count":1,"title":["Analytical Model for High\u2013Level Area Estimation of FPGA Design"],"prefix":"10.4018","volume":"7","author":[{"given":"Rachna","family":"Singh","sequence":"first","affiliation":[{"name":"BCE, Bhopal, India"}]},{"given":"Arvind","family":"Rajawat","sequence":"additional","affiliation":[{"name":"MANIT, Bhopal, India"}]}],"member":"2432","reference":[{"key":"IJERTCS.2016070103-0","doi-asserted-by":"crossref","unstructured":"Abdelhalim, M., & Habib, D. (2008). Fast FPGA-based Area and Latency Estimation for a Novel Hardware\/Software Partitioning Scheme. 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Proceedings of 1998 Asia and South Pacific Design Automation Conference, Yokohama, Japan (pp. 353\u2013360)."},{"key":"IJERTCS.2016070103-6","first-page":"1","article-title":"Hardware Performance Estimation by Dynamic Scheduling.","author":"A. M. P.Gonz\u00e1lez","year":"2011","journal-title":"Proceeding of Forum on specification and Design Languages"},{"key":"IJERTCS.2016070103-7","doi-asserted-by":"publisher","DOI":"10.1145\/1124713.1124721"},{"key":"IJERTCS.2016070103-8","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339214"},{"key":"IJERTCS.2016070103-9","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2015.2421319"},{"key":"IJERTCS.2016070103-10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882119"},{"key":"IJERTCS.2016070103-11","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117232"},{"key":"IJERTCS.2016070103-12","doi-asserted-by":"crossref","unstructured":"Nayak, A., Haldar, M., Choudhary, A., & Banerjee, P. (2002). Accurate Area and Delay Estimators for FPGAs. Proceedings of the Automation and Test in Europe Conference and Exhibition DATE\u201902, Paris, France (pp. 862-869).","DOI":"10.1109\/DATE.2002.998400"},{"key":"IJERTCS.2016070103-13","doi-asserted-by":"crossref","unstructured":"Niu, X., Wu, Y., & Zhang, B. (2013). Rapid FPGA-based Delay Estimation for the Hardware\/Software Partitioning. Journal of networks, 8(5), 1183-1190.","DOI":"10.4304\/jnw.8.5.1183-1190"},{"key":"IJERTCS.2016070103-14","doi-asserted-by":"crossref","unstructured":"Niu, X., Wu, Y., Zhang, B., Gu, G., & Zhang, G. (2013). Auto Estimation Model of FPGA based Delay for the Hardware\/Software Partitioning. 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