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To achieve this, the comparison of results for high-level, low-level and SystemC NoC simulation is given on the example of \u201chot spots\u201d and the geometric shape of regular NoC topologies effect on their productivity.<\/p>","DOI":"10.4018\/ijertcs.2018070102","type":"journal-article","created":{"date-parts":[[2018,4,16]],"date-time":"2018-04-16T12:58:03Z","timestamp":1523883483000},"page":"18-31","source":"Crossref","is-referenced-by-count":12,"title":["SystemC Language Usage as the Alternative to the HDL and High-level Modeling for NoC Simulation"],"prefix":"10.4018","volume":"9","author":[{"given":"Aleksandr","family":"Romanov","sequence":"first","affiliation":[{"name":"National Research University Higher School of Economics, Moscow, Russia"}]},{"given":"Alexander","family":"Ivannikov","sequence":"additional","affiliation":[{"name":"The Institute for Design Problems in Microelectronics of Russian Academy of Sciences, Moscow, Russia"}]}],"member":"2432","reference":[{"key":"IJERTCS.2018070102-0","doi-asserted-by":"publisher","DOI":"10.1109\/EWDTS.2010.5742036"},{"key":"IJERTCS.2018070102-1","unstructured":"Ayough, L. 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