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An intelligent embedded data cache and a dynamic reconfigurable intelligent embedded data cache have been implemented using Verilog 2001 and tested for cache performance. Data collected by enabling the cache with two different replacement strategies have shown that the hit rate improves by 40% when compared to LRU and 21% when compared to MRU for sequential applications which will significantly improve performance of embedded real time application.<\/jats:p>","DOI":"10.4018\/ijertcs.2019040106","type":"journal-article","created":{"date-parts":[[2019,3,20]],"date-time":"2019-03-20T13:29:02Z","timestamp":1553088542000},"page":"87-107","source":"Crossref","is-referenced-by-count":0,"title":["Design of an Intelligent Data Cache with Replacement Policy"],"prefix":"10.4018","volume":"10","author":[{"given":"B. Shameedha","family":"Begum","sequence":"first","affiliation":[{"name":"National Institute of Technology Tiruchirappalli, Tiruchirappalli, India"}]},{"given":"N.","family":"Ramasubramanian","sequence":"additional","affiliation":[{"name":"National Institute of Technology Tiruchirappalli, Tiruchirappalli, India"}]}],"member":"2432","reference":[{"key":"IJERTCS.2019040106-0","doi-asserted-by":"crossref","unstructured":"Crisu, D. (1999). An architectural survey and modeling of data cache memories in Verilog HDL. In CAS'99 Proceedings, Romania (pp. 139-142). IEEE.","DOI":"10.1109\/SMICND.1999.810448"},{"key":"IJERTCS.2019040106-1","unstructured":"Jacob, B. (1999). Cache design for embedded real-time systems."},{"key":"IJERTCS.2019040106-2","author":"J. L.Hennessy","year":"2011","journal-title":"Computer architecture: a quantitative approach"},{"key":"IJERTCS.2019040106-3","doi-asserted-by":"crossref","unstructured":"Bani, R. R., Mohanty, S. P., Kougianos, E., & Thakral, G. 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