{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,14]],"date-time":"2025-05-14T12:01:26Z","timestamp":1747224086017,"version":"3.40.5"},"reference-count":33,"publisher":"IGI Global","issue":"1","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,6,29]]},"abstract":"<p>Because of SRAM sensitivity to radiation, SRAM-based FPGA systems deployed in harsh environments require error mitigation methods to reduce their overall downtime. This paper presents a fault-tolerant reconfigurable imaging system that relies on the DPR feature for correcting errors in the configuration memory and loading camera system IPs. The system reliability is evaluated by injecting faults in the FPGA configuration memory at runtime using the Xilinx SEM IP. The faults are injected internally using the Internal Configuration Access Port (ICAP), which is shared between the fault injection core and system parts. The results showed that 95% of the errors can by corrected automatically. This paper also proposes a fast-Built-in-Self-Test (BIST) mitigation technique to reduce the overall downtime in case of errors. This technique can reduce the recovery time by 80%. Moreover, Triple Modular Redundancy (TMR) is used to increase the overall reliability without significantly increasing the resource overhead.<\/p>","DOI":"10.4018\/ijertcs.302108","type":"journal-article","created":{"date-parts":[[2022,5,5]],"date-time":"2022-05-05T02:05:29Z","timestamp":1651716329000},"page":"1-17","source":"Crossref","is-referenced-by-count":0,"title":["Design and Implementation of a Reliable Reconfigurable Imaging System"],"prefix":"10.4018","volume":"13","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0842-7426","authenticated-orcid":true,"given":"Jalal","family":"Khalifat","sequence":"first","affiliation":[{"name":"University of Bahrain, Bahrain"}]},{"given":"Ali","family":"Ebrahim","sequence":"additional","affiliation":[{"name":"University of Bahrain, Bahrain"}]}],"member":"2432","reference":[{"key":"IJERTCS.302108-0","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2017.8046378"},{"key":"IJERTCS.302108-1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2018.2824821"},{"key":"IJERTCS.302108-2","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2017.2666843"},{"key":"IJERTCS.302108-3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.2969094"},{"key":"IJERTCS.302108-4","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2008.2001422"},{"key":"IJERTCS.302108-5","unstructured":"Bridgford B., Carmichael C., & Tseng, C. W. (2008). Single-Event Upset Mitigation Selection Guide. Xilinx Ap-plication Note, XAPP987 (v1.0)."},{"journal-title":"Scan-Based Soft Error Mitigation of Configuration Memory in Xilinx 7-Series FPGA Devices. IP solutions","year":"2015","author":"E.Crabill","key":"IJERTCS.302108-6"},{"key":"IJERTCS.302108-7","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2012.6268660"},{"key":"IJERTCS.302108-8","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2013.6604243"},{"key":"IJERTCS.302108-9","unstructured":"Grand View Research. (2020). Global FPGA market by application Expected to Reach USD 9,882.5 Million by 2020. Available: https:\/\/www.grandviewresearch.com\/press-release\/global-fpga-market"},{"key":"IJERTCS.302108-10","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2008.4526471"},{"key":"IJERTCS.302108-11","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2021.3070856"},{"key":"IJERTCS.302108-12","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2015.7231170"},{"key":"IJERTCS.302108-13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3010743"},{"key":"IJERTCS.302108-14","doi-asserted-by":"publisher","DOI":"10.4018\/978-1-60960-212-3.ch010"},{"key":"IJERTCS.302108-15","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.229"},{"key":"IJERTCS.302108-16","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2016.2603918"},{"key":"IJERTCS.302108-17","unstructured":"Manners, D. (2010). FPGA Market Soaring To $4bn In 2010, says Gavrielov. Available: https:\/\/www.electronicsweekly.com\/news\/products\/fpga-news\/fpga-market-soaring-to-4bn-in-2010-says-gavrielov-2010-05\/"},{"key":"IJERTCS.302108-18","first-page":"226","article-title":"Improving FPGA design robustness with par-tial TMR","author":"B.Pratt","year":"2006","journal-title":"Proc. of IEEE International Reliability Physics Symposium (IRPS)"},{"key":"IJERTCS.302108-19","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2017.2757978"},{"key":"IJERTCS.302108-20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCONS.2018.8662913"},{"key":"IJERTCS.302108-21","unstructured":"Srikanth, E. (2018). Zynq-7000 AP SoC Low Power Techniques part 2 - Measuring ZC702 Power using TI Fusion Power Designer Tech Tip. Available: http:\/\/www.wiki.xilinx.com\/Zynq-7000+AP+SoC+Low+Power+Techniques+part+2++Measuring+ZC702+Power+using+TI+Fusion+Power+Designer+Tech+Tip"},{"key":"IJERTCS.302108-22","doi-asserted-by":"publisher","DOI":"10.4018\/IJERTCS.2015010102"},{"key":"IJERTCS.302108-23","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2019.000-5"},{"key":"IJERTCS.302108-24","doi-asserted-by":"publisher","DOI":"10.1109\/SpaceComp.2019.00008"},{"key":"IJERTCS.302108-25","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577349"},{"key":"IJERTCS.302108-26","unstructured":"Xilinx. (2001). IEEE 802.3 Cyclic Redundancy Check. Xilinx Application Note: XAPP209."},{"key":"IJERTCS.302108-27","unstructured":"Xilinx. (2015). 7 Series FPGAs Mitigation Single-Event Upsets. Xilinx White Paper: WP395 (v1.1)."},{"key":"IJERTCS.302108-28","unstructured":"Xilinx. (2017). Vivado Design Suite user guide, Partial Reconfiguration. Xilinx Document: UG909 (v2017.1)."},{"key":"IJERTCS.302108-29","unstructured":"Xilinx. (2018). Soft Error Mitigation Controller V4.1- LogiCORE IP Product Guide. Xilinx Documnet: PG036."},{"key":"IJERTCS.302108-30","doi-asserted-by":"publisher","DOI":"10.1109\/ITC44170.2019.9000155"},{"key":"IJERTCS.302108-31","doi-asserted-by":"publisher","DOI":"10.1109\/ITC44778.2020.9325249"},{"key":"IJERTCS.302108-32","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2018.8565046"}],"container-title":["International Journal of Embedded and Real-Time Communication Systems"],"original-title":[],"language":"ng","link":[{"URL":"https:\/\/www.igi-global.com\/viewtitle.aspx?TitleId=302108","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,16]],"date-time":"2023-01-16T23:28:22Z","timestamp":1673911702000},"score":1,"resource":{"primary":{"URL":"https:\/\/services.igi-global.com\/resolvedoi\/resolve.aspx?doi=10.4018\/IJERTCS.302108"}},"subtitle":[""],"short-title":[],"issued":{"date-parts":[[2022,6,29]]},"references-count":33,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2022,1]]}},"URL":"https:\/\/doi.org\/10.4018\/ijertcs.302108","relation":{},"ISSN":["1947-3176","1947-3184"],"issn-type":[{"type":"print","value":"1947-3176"},{"type":"electronic","value":"1947-3184"}],"subject":[],"published":{"date-parts":[[2022,6,29]]}}}